MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 84
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Instruction Set Summary
2.6.1 Additions to the Instruction Set Architecture
The original ColdFire instruction set architecture (ISA) was derived from the M68000
Family opcodes based on extensive analysis of embedded application code. After the initial
ColdFire compilers were created, developers identified ISA additions that would enhance
both code density and overall performance. Additionally, as users implemented
ColdFire-based designs into a wide range of embedded systems, they identified frequently
used instruction sequences that could be improved by the creation of new instructions. This
observation was especially prevalent in development environments that made use of
substantial amounts of assembly language code.
The original ISA definition minimized the support for instructions referencing byte and
word operands. Full support for the MOVE.B and MOVEC.W instructions was provided,
but clr (clear) and tst (test) are the only other opcodes supporting these data types. Based
on input from compiler writers and system users, a set of instruction enhancements was
proposed that address the two following areas:
The following list summarizes new and enhanced instructions of Revision_B ISA:
2-18
Instruction
• Enhanced support for byte and word-sized operands through new move operations
• Enhanced support for position-independent code
• New instructions:
C
N
V
X
Z
— INTOUCH loads blocks of instructions to be locked in the instruction cache
— MOV3Q.L moves 3-bit immediate data to the destination location
— MVS.{B,W} sign-extends the source operand and moves it to the destination
— MVZ.{B,W} zero-fills the source operand and moves it to the destination
— SATS.L updates the destination register depending on CCR[V] and bit 31 of the
— TAS.B performs an indivisible read-modify-write cycle to test and set the
register
register
register
addressed memory byte.
Carry
Negative
Overflow
Extend
Zero
Table 2-6. Notational Conventions (Continued)
Condition Code Register Bit Names
MCF5407 User’s Manual
Operand Syntax
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