MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 326
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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DMA Controller Module Functional Description
The DAR should contain the destination (write) address. If the transfer is from a peripheral
device to memory, or memory to memory, the DAR is loaded with the starting address of
the data block to be written. If the transfer is from memory to a peripheral device, DAR is
loaded with the address of the peripheral data register. This address can be any aligned byte
address. DAR is not used in single-address mode.
SAR and DAR change after each cycle depending on DCR[SSIZE,DSIZE,SINC,DINC]
and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword,
or line transfers, respectively. If the address register is programmed to remain unchanged
(no count), the register is not incremented after the data transfer.
BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented
by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSR must be
cleared for channel startup.
As soon as the channel has been initialized, it is started by writing a one to DCR[START]
or asserting DREQ, depending on the status of DCR[EEXT]. Programming the channel for
internal request causes the channel to request the bus and start transferring data
immediately. If the channel is programmed for external request, DREQ must be asserted
before the channel requests the bus.
Changes to DCR are effective immediately while the channel is active. To avoid problems
with changing a DMA channel setup, write a one to DSR[DONE] to stop the DMA channel.
12.5.4 Data Transfer
This section includes timing diagrams that illustrate the interaction of signals in DMA data
transfers. It also describes auto-alignment and bandwidth control.
12.5.4.1 External Request and Acknowledge Operation
Channels 0 and 1 initiate transfers to an external module by means of DREQ[1:0]. The
request for channels 2 and 3 are connected internally to the UART0 and UART1 interrupt
signals, respectively. If DCR[EEXT] = 1 and the channel is idle, the DMA initiates a
transfer when DREQ is asserted.
Figure 12-11 shows the minimum 4-clock cycle delay from when DREQ is sampled
asserted to when a DMA bus cycle begins. This delay may be longer, depending on DMA
priority, bus arbitration, DRAM refresh operations, and other factors.
MCF5407 User’s Manual
12-14
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