MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 97

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.8 Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. Differences
from previous M68000 Family processors include the following:
ColdFire processors use an instruction restart exception model but require more software
support to recover from certain access errors. See Table 2-19 for details.
Exception processing can be defined as the time from the detection of the fault condition
until the fetch of the first handler instruction has been initiated. It is comprised of the
following four major steps:
ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address
boundary; see Table 2-19. The table contains 256 exception vectors where the first 64 are
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single, self-aligning system stack pointer
1. The processor makes an internal copy of the SR and then enters supervisor mode by
2. The processor determines the exception vector number. For all faults except
3. The processor saves the current context by creating an exception stack frame on the
4. The processor acquires the address of the first instruction of the exception handler.
setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an
interrupt exception also forces SR[M] to be cleared and the interrupt priority mask
to be set to the level of the current interrupt request.
interrupts, the processor performs this calculation based on the exception type. For
interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to
obtain the vector number from a peripheral device. The IACK cycle is mapped to a
special acknowledge address space with the interrupt level encoded in the address.
system stack. ColdFire processors support a single stack pointer in the A7 address
register; therefore, there is no notion of separate supervisor and user stack pointers.
As a result, the exception stack frame is created at a 0-modulo-4 address on the top
of the current system stack. Additionally, the processor uses a simplified
fixed-length stack frame for all exceptions. The exception type determines whether
the program counter in the exception stack frame defines the address of the faulting
instruction (fault) or of the next instruction to be executed (next).
The exception vector table is aligned on a 1-Mbyte boundary. This instruction
address is obtained by fetching a value from the table at the address defined in the
vector base register. The index into the exception table is calculated as
4 x vector_number. When the index value is generated, the vector table contents
determine the address of the first instruction of the desired handler. After the fetch
of the first opcode of the handler is initiated, exception processing terminates and
normal instruction processing continues in the handler.
Chapter 2. ColdFire Core
Exception Processing Overview
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