MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 51

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ColdFire Module Description
1.2.1 Process
The MCF5407 is manufactured in a 0.22-µ CMOS process with quad-layer-metal routing
technology. This process combines the high performance and low power needed for
embedded system applications. Inputs are 3.3-V tolerant; outputs are CMOS or open-drain
CMOS with outputs operating from VDD + 0.5 V to GND - 0.5 V, with guaranteed
TTL-level specifications.
1.3 ColdFire Module Description
The following sections provide overviews of the various modules incorporated in the
MCF5407.
1.3.1 ColdFire Core
The Version 4 ColdFire core consists of two independent and decoupled pipelines to
maximize performance—the instruction fetch pipeline (IFP) and the operand execution
pipeline (OEP).
1.3.1.1 Instruction Fetch Pipeline (IFP)
The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the
operand execution pipeline (OEP). Because the fetch and execution pipelines are decoupled
by a ten-instruction FIFO buffer, the fetch mechanism can prefetch instructions in advance
of their use by the OEP, thereby minimizing the time stalled waiting for instructions. To
maximize the performance of conditional branch instructions, the Version 4 IFP
implements a sophisticated two-level acceleration mechanism.
The first level is an 8-entry, direct-mapped branch cache with a 2-bit prediction state
(strongly/weakly, taken/not-taken) for each entry. The branch cache implements instruction
folding techniques. These allow conditional branch instructions that are predicted correctly
as taken to execute in zero cycles.
For those conditional branches with no information in the branch cache, a second-level,
direct-mapped prediction table containing 128 entries is accessed. Again, each entry uses
the same 2-bit prediction state definition as the branch cache. This branch prediction state
is then used to predict the direction of prefetched conditional branch instructions.
Other change-of-flow instructions, including unconditional branches, jumps, and
subroutine calls, use a similar mechanism where the IFP calculates the target address. The
performance of subroutine return instructions is improved through the use of a four-entry,
LIFO return stack.
In all cases, these mechanisms allow the IFP to redirect the fetch stream down the path
predicted to be taken well in advance of the actual instruction execution. The result is
significantly improved performance.
Chapter 1. Overview
1-7