MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 455
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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In Figure 18-28, the external device is master during C1 and C2. It releases bus control in
C3 by asserting BG to the MCF5407. During C4 and C5, the MCF5407 is implicit master
because no internal access is pending. In C5, an internal bus request becomes pending,
causing the MCF5407 to become explicit bus master in C6 by asserting BD. In C7, the
external device removes the bus grant to the MCF5407. The MCF5407 does not release the
bus (the MCF5407 continues to assert BD) until the transfer ends.
Figure 18-29 is a MCF5407 bus arbitration state diagram. States are described in
Table 18-6.
SIZ[1:0], TM[2:0]
A[31:0], TT[1:0]
Figure 18-28. Two-Wire Implicit and Explicit Bus Mastership
CLKIN
D[31:0]
The MCF5407 can start a transfer in the clock cycle after BG
is asserted. The external master must not assert BG to the
MCF5407 while driving the bus or the part may be damaged.
R/W
TIP
BG
BD
AS
TS
TA
C1
External Master
C2
Chapter 18. Bus Operation
C3
NOTE:
C4
Mastership
Implicit
General Operation of External Master Transfers
C5
C6
MCF5407
C7
Mastership
Explicit
C8
C9
18-27
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