MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 52
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Module Description
1.3.1.2 Operand Execution Pipeline (OEP)
The prefetched instruction stream is gated from the FIFO buffer into the five-stage OEP.
The OEP consists of two, traditional two-stage RISC compute engines with a register file
access feeding an arithmetic/logic unit (ALU). The compute engine located at the top of the
OEP is typically used for operand memory address calculations (the address ALU), while
the compute engine located at the bottom of the pipeline is used for instruction execution
(the execution ALU). The resulting structure provides 3.9 Gbytes/S data operand
bandwidth at 162 MHz to the two compute engines and supports single-cycle execution
speeds for most instructions, including all load, store, and most embedded-load operations.
In response to users and developers’ comments, the V4 design supports execution of the
ColdFire Revision B instruction set, which adds a small number of new instructions to
improve performance and code density.
The OEP also implements two advanced performance features. It dynamically determines
the appropriate location of instruction execution (either in the address ALU or the execution
ALU) based on the pipeline state. The address compute engine, in conjunction with register
renaming resources, can be used to execute a number of heavily-used opcodes and forward
the results to subsequent instructions without any pipeline stalls. Additionally, the OEP
implements instruction folding techniques involving MOVE instructions so that two
instructions can be issued in a single machine cycle. The resulting microarchitecture
approaches the performance of a full superscalar implementation, but at a much lower
silicon cost.
1.3.1.3 MAC Module
The MAC unit provides signal processing capabilities for the MCF5407 in a variety of
applications including digital audio and servo control. Integrated as an execution unit in the
processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for
16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in
addition to a full set of extensions for signed and unsigned integers, plus signed, fixed-point
fractional input operands.
1.3.1.4 Integer Divide Module
Integrated into the OEP, the divide module performs operations using signed and unsigned
integers. The module supports word and longword divides producing quotients and/or
remainders.
1.3.2 Harvard Architecture
A Harvard memory architecture implements separate instruction and data buses to the
processor-local memories, removing conflicts between instruction fetches and operand
accesses.
MCF5407 User’s Manual
1-8
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