MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 162

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Real-Time Trace Support
5.3.1 Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may
be displayed on PSTDDATA depending on the CSR settings. CSR also controls the number
of address bytes displayed, which is indicated by the PST marker value immediately
preceding the DDATA nibble that begins the data output.
Bytes are displayed in least-to-most-significant order. The processor captures only those
target addresses associated with taken branches which use a variant addressing mode, that
is, RTE and RTS instructions, JMP and JSR instructions using address register indirect or
indexed addressing modes, and all exception vectors.
The simplest example of a branch instruction using a variant address is the compiled code
for a C language case statement. Typically, the evaluation of this statement uses the variable
of an expression as an index into a table of offsets, where each offset points to a unique case
within the structure. For such change-of-flow operations, the MCF5407 uses the debug pins
to output the following sequence of information on successive processor clock cycles:
Another example of a variant branch instruction would be a JMP (A0) instruction.
Figure 5-4 shows when the PSTDDATA outputs that indicate when a JMP (A0) executed,
assuming the CSR was programmed to display the lower 2 bytes of an address.
PSTDDATA is driven two nibbles at a time with a 0x59; 0x5 indicates a taken branch and
the marker value 0x9 indicates a 2-byte address. Thus, the remaining 4 nibbles display the
lower 2 bytes of address register A0 in least-to-most-significant nibble order. The
PSTDDATA output after the JMP instruction continues with the next instruction.
5-6
1. Use PSTDDATA (0x5) to identify that a taken branch was executed.
2. Optionally signal the target address to be displayed sequentially on the PSTDDATA
3. The new target address is optionally available on subsequent cycles using the
pins. Encodings 0x9–0xB identify the number of bytes displayed.
PSTDDATA port. The number of bytes of the target address displayed on this port
is configurable (2, 3, or 4 bytes).
PSTDDATA
PSTCLK
Figure 5-4. Example JMP Instruction Output on PSTDDATA
PCLK
0x59
MCF5407 User’s Manual
A0[3–0,7–4]
A0[11–8,15–12]