MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 18
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Paragraph
Number
18.4.7.4
18.5
18.6
18.7
18.7.1
18.7.2
18.8
18.8.1
18.9
18.9.1
18.9.2
18.10
18.10.1
18.10.2
19.1
19.2
19.3
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.5
19.6
19.7
20.1
20.1.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
xviii
Misaligned Operands ...................................................................................... 18-16
Bus Errors ....................................................................................................... 18-17
Interrupt Exceptions........................................................................................ 18-17
Bus Arbitration................................................................................................ 18-20
General Operation of External Master Transfers............................................ 18-21
Reset Operation............................................................................................... 18-33
Overview........................................................................................................... 19-1
TAP Controller.................................................................................................. 19-3
JTAG Register Descriptions ............................................................................. 19-4
Restrictions ..................................................................................................... 19-10
Disabling IEEE Standard 1149.1 Operation ................................................... 19-10
Obtaining the IEEE Standard 1149.1.............................................................. 19-11
General Parameters ........................................................................................... 20-1
Clock Timing Specifications............................................................................. 20-4
Input/Output AC Timing Specifications........................................................... 20-6
Reset Timing Specifications ........................................................................... 20-15
Debug AC Timing Specifications................................................................... 20-16
Timer Module AC Timing Specifications ...................................................... 20-17
I
UART Module AC Timing Specifications ..................................................... 20-19
JTAG Signal Descriptions ............................................................................... 19-2
2
C Input/Output Timing Specifications......................................................... 20-18
Level 7 Interrupts........................................................................................ 18-18
Interrupt-Acknowledge Cycle..................................................................... 18-19
Bus Arbitration Signals............................................................................... 18-21
Two-Device Bus Arbitration Protocol (Two-Wire Mode) ......................... 18-25
Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... 18-29
Master Reset ............................................................................................... 18-34
Software Watchdog Reset........................................................................... 18-35
IDCODE Register ......................................................................................... 19-6
JTAG Boundary-Scan Register .................................................................... 19-7
JTAG Bypass Register................................................................................ 19-10
Supply Voltage Sequencing and Separation Cautions.................................. 20-3
JTAG Instruction Shift Register .................................................................. 19-5
Transfers Using Mixed Port Sizes .......................................................... 18-15
IEEE 1149.1 Test Access Port (JTAG)
Electrical Specifications
MCF5407 User’s Manual
CONTENTS
Chapter 19
Chapter 20
Title
Number
Page
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