MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 539

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

M
MAC
Mask registers
MBAR, 6-4
Mechanical data, 16-1
Memory
Modules, 1-7
MOVE instructions timing, 2-25
O
Opcodes
P
Parallel port
Pin assignment register, 6-10, 15-1
signal descriptions, 19-2
TAP controller, 19-3
test logic disabling, 19-10
data representation, 3-4
hardware support, 2-5
instruction execution timings, 3-5
instruction set summary, 3-4
operation, 3-3
programming model, 2-10, 3-2
DRAM, 11-7, 11-22
case drawing, 16-9
diagram, 16-8
pinout, 16-1
integer data formats, 2-14
SIM register, 6-3
base address register, 2-12
core description, 1-7
debug, 2-6
DMA controller, 1-9
DRAM controller, 1-9
I
PLL, 1-13
system interface, 1-11
Timer, 1-11
UARTs, 1-10
illegal handling, 2-5
code example, 15-4
data direction register, 15-2
data register, 15-2
operation, 15-1
2
C, 1-11
16-bit parallel port, 1-12
chip selects, 1-11
debug, 1-12
external bus, 1-11
interrupt controller, 1-12
JTAG, 1-12
INDEX
Index
Pipelines, 2-2
PLL, 7-2
Power supply
Program counter, 2-9
Programming models
R
RAM base address registers, 2-12
Registers
instruction fetch, 2-4
operand execution, 2-4
clock control for STOP, 6-10
clock frequency relationships, 7-4
clock-multiplied, 2-2
control register, 7-3
modes
operation, 7-2
overview, 7-1
port list, 7-4
power supply filter circuit, 7-6
reset/initialization, 7-2
timing relationships, 7-4
filter circuit, 7-6
MAC, 2-10
overview, 2-7
registers, 1-15
SIM, 6-3
summary, B-1
supervisor, 2-10
user, 2-8
A0–A6, 2-9
A7, 2-9
AATR, 5-10
access control, 2-12
address, 2-9
AVR, 9-5
BAAR, 5-12
bus master park, 6-11
cache configuration, 2-12
CACR, 2-12
CCR, 2-9
chip-select
condition code, 2-9
CSR, 5-13
D0–D7, 2-8
data, 2-8, A-13
DMA byte count, 12-7
DMA source address, 12-7
DRAM
normal, 7-2
reduced power, 7-3
control, 10-8
mask, 10-7
module, 10-5
Index-3