MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 80

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Organization of Data in Registers
operands are sign-extended to 32 bits and then used in the operation with anaddress register
destination. When an address register is a destination, the entire register is affected,
regardless of the operation size. Figure 2-8 shows integer formats for address registers.
The size of control registers varies according to function. Some have undefined bits
reserved for future definition by Motorola. Those particular bits read as zeros and must be
written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations. For all CCR operations, the
upper byte is read as all zeros and is ignored when written, regardless of privilege mode.
2.4.2 Organization of Integer Data Formats in Memory
All ColdFire processors use a big-endian addressing scheme. The byte-addressable
organization of memory allows lower addresses to correspond to higher order bytes. The
address N of a longword data item corresponds to the address of the high-order word. The
lower order word is located at address N + 2. The address N of a word data item corresponds
to the address of the high-order byte. The lower order byte is located at address N + 1. This
organization is shown in Figure 2-9.
2-14
31
Byte 0xFFFF_FFFC
Byte 0x0000_0000
Byte 0x0000_0004
Figure 2-8. Organization of Integer Data Formats in Address Registers
31
31
Word 0xFFFF_FFFC
Word 0x0000_0000
Word 0x0000_0004
Sign-Extended
Figure 2-9. Memory Operand Addressing
23
Byte 0xFFFF_FFFD
Byte 0x0000_0001
Byte 0x0000_0005
Full 32-Bit Address Operand
MCF5407 User’s Manual
Longword 0xFFFF_FFFC
Longword 0x0000_0000
Longword 0x0000_0004
16
.
.
.
15
15
Byte 0xFFFF_FFFE
Byte 0x0000_0002
Byte 0x0000_0006
16-Bit Address Operand
Word 0xFFFF_FFFE
Word 0x0000_0002
Word 0x0000_0006
7
Byte 0xFFFF_FFFF
Byte 0x0000_0003
Byte 0x0000_0007
0
0
0