DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 123

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.1
As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exception
handling requests are accepted at all times in program execution state.
The exception source, the stack structure, and the operation of the CPU vary depending on the
interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 4.1
4.2
Different vector address is assigned to each exception source. Table 4.2 lists the exception sources
and their vector addresses.
Priority
High
Low
Exception Handling Types and Priority
Exception Sources and Exception Vector Table
Exception Type
Reset
Trace
Interrupt
Trap instruction
(TRAPA)
Exception Types and Priority
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
and MRES pins, or when the watchdog timer overflows. The
CPU enters the power-on reset state when the RES pin is low.
The CPU enters the manual reset state when the MRES pin is
low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1. Trace is enabled
only in interrupt control mode 2. Trace exception handling is
not executed after execution of an RTE instruction.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on completion
of reset exception handling.
Started by execution of a trap instruction (TRAPA). Trap
instruction exception handling requests are accepted at all
times in program execution state.
Rev. 6.00 Sep. 24, 2009 Page 75 of 928
Section 4 Exception Handling
REJ09B0099-0600