DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 564

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 A/D Converter
15.3
The A/D converter has the following registers. For details on the module stop control register, see
section 22.1.2, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
15.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each analog input
channel, are shown in table 15.2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. Therefore,
when reading ADDR, read only the upper byte, or read in word unit.
Table 15.2 Analog Input Channels and Corresponding ADDR Registers
Rev. 6.00 Sep. 24, 2009 Page 516 of 928
REJ09B0099-0600
Group 0
(CH2 = 0)
AN0
AN1
AN2
AN3
Channel Set 0 (CH3 = 0)
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
Group 1
(CH2 = 1)
AN4
AN5
AN6
AN7
Analog Input Channel
Channel Set 1 (CH3 = 1)
Group 0
(CH2 = 0)
AN8
AN9
AN10
AN11
Group 1
(CH2 = 1)
AN12
AN13
AN14
AN15
A/D Data Register to be
Stored Results of A/D
Conversion
ADDRA
ADDRB
ADDRC
ADDRD