DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 211

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.9
This LSI can release the external bus in response to a bus mastership request from an external
device. In the external bus mastership released state, the internal bus master continues to operate
as long as there is no external access.
In external extended mode, the bus mastership can be released to an external device by setting the
BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus mastership request to
this LSI. When the BREQ pin is sampled, the BACK pin is driven low at the prescribed timing,
and the address bus, data bus, and bus control signals are placed in the high-impedance state,
establishing the external bus mastership released state.
In the external bus mastership released state, an internal bus master can perform accesses using the
internal bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus mastership request from the external bus master
to be dropped.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus mastership released state is terminated.
In the event of simultaneous external bus mastership release request and external access request
generation, the order of priority is as follows:
Table 7.5 shows the pin states in the external bus mastership released state.
Table 7.5
Pins
A23 to A0
D15 to D0
CSn
AS
RD
HWR
LWR
(High) External bus mastership release > Internal bus master external access (Low)
Bus Release
Pin States in Bus Mastership Released State
Pin State
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
Rev. 6.00 Sep. 24, 2009 Page 163 of 928
Section 7 Bus Controller
REJ09B0099-0600