DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 324

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.1
The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR
registers, one for each channel (channels 0 to 5). TCR register settings should be conducted only
when TCNT operation is stopped.
Rev. 6.00 Sep. 24, 2009 Page 276 of 928
REJ09B0099-0600
Bit
7
6
5
4
3
2
1
0
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
Initial
value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source. See
tables 10.3 and 10.4 for details.
Clock Edge 1 and 0
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock period is
halved (e.g. φ/4 both edges = φ/2 rising edge). If phase
counting mode is used on channels 1, 2, 4, and 5, this
setting is ignored and the phase counting mode setting
has priority. Internal clock edge selection is valid when the
input clock is φ/4 or slower. This setting is ignored if the
input clock is φ/1, or when overflow/underflow of another
channel is selected. (The clock is counted at the falling
edge when φ/1 is selected.)
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
Legend:
X: Don’t care
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 10.5 to 10.10 for details.