DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 368

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
10.4.5
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
• PWM mode 2
Rev. 6.00 Sep. 24, 2009 Page 320 of 928
REJ09B0099-0600
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by the IOA0 to IOA3 bits and IOC0 to IOC3 bits in
TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by the IOB0 to IOB3 bits and IOD0 to IOD3 bits in TIOR is output at compare
matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values
of paired TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
TCLKA
TCLKB
TCNT_2
TCNT_1
PWM Modes
Figure 10.19 Example of Cascaded Operation (2)
FFFD
0000
FFFE
FFFF
0000
0001
0001
0002
0001
0000
FFFF
0000