DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 658

IC H8S/2506 MCU FLASH 176-LFBGA

DF2506BR26DV

Manufacturer Part Number
DF2506BR26DV
Description
IC H8S/2506 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2506BR26DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2506BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 Controller Area Network (HCAN) [H8S/2556 Group]
• Module stop mode can be set
• DTC can be activated by the reception of a message (only in HCAN mailbox 0)
• Message Buffer Interface (MBI)
• Microprocessor Interface (MPI)
• CAN Data Link Controller (CDLC)
Rev. 6.00 Sep. 24, 2009 Page 610 of 928
REJ09B0099-0600
Bus off status
HCAN configuration mode
HCAN sleep mode
HCAN halt mode
The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN
transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU.
For receive messages, the data received by the CDLC is stored automatically.
The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN
internal data, status, and so forth.
The CDLC transmits and receives of messages conforming to the Bosch CAN Ver. 2.0B active
standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as
well as CRC checking, bus arbitration, and other functions.
MBI
Message buffer
MPI
Microprocessor interface
HCAN
Mailboxes
Message control
Message data
MC0 to MC15,
MD0 to MD15
CPU interface
Control register
Status register
Figure 18.1 HCAN Block Diagram
LAFM
Bosch CAN 2.0B active
Data Link Controller
(CDLC)
CAN
Tx buffer
Rx buffer
HTxD
HRxD

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