DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 645

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Because the above settings are performed before frame reception, the length of data to be received
cannot be determined. Accordingly, the maximum number of transfer bytes in one frame is
specified as the DTC transfer count.
If the DTC is specified after reception starts, the above settings are performed in the receive start
detection (RxS) interrupt handling routine. In this case, the transfer count must be the same value
as the contents of the IEBus receive message length register (IERBFL).
(3)
Figure 17.11 shows the master reception flow. Numbers in the following description correspond to
the number in figure 17.11. In this example, the DTC is specified when the frame reception starts.
1. After the IEB has been initialized, a master communications request command is issued from
2. The CMX flag is cleared when the slave reception is completed, the master communications
3. If the arbitration is won, the master address, slave address, and control field will be
4. The message length field is received from the slave unit. If no parity error is detected and
5. When the first data is received, the RxRDY flag is set to 1. A DTC transfer request by IERxI
6. Similarly, the above data field receive and load operations are repeated.
7. When the last data is received, the DTC completes the data transfer for the specified number of
8. When the DTC transfer has been completed, an RxRDY interrupt (IERxI) is issued to the
IECMR. During slave reception, the command execution status flag (CMX) in IEFLG is set
and the master communications request will not be issued.
command is executed, and the MRQ flag is set.
transmitted. An error generated before the control field transmission will be handled as a
transmission error. In this case, the TxE flag is set and the error contents will be reflected in
IETEF.
reception is performed correctly, the receive start detection flag (RxS) is set to 1. If a parity
error occurs, it is handled as a receive error. A receive start detection (RxS) interrupt (receive
status interrupt (IERSI)) occurs and the DTC initialization described in (2) is performed. After
DTC initialization, the RxS flag is cleared to 0.
occurs and the DTC loads data from the IEBus receive buffer register (IERBR) and clears the
RxRDY flag.
bytes after loading the receive data to the RAM. In this case, the DTC does not clear the
RxRDY flag. It, however, clears the DTC enable register G (DTCEG). Accordingly, hereafter,
no transfer request will be issued to the DTC.
CPU. In this interrupt handling routine, the RxRDY flag is cleared.
Master Reception Flow
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 597 of 928
REJ09B0099-0600