DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 219

IC H8S/2506 MCU FLASH 176-LFBGA

DF2506BR26DV

Manufacturer Part Number
DF2506BR26DV
Description
IC H8S/2506 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2506BR26DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2506BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Legend:
X:
8.2.2
MRB is an 8-bit register that selects the DTC operating mode.
Bit
0
Bit
7
6
5 to 0
Don’t care
Bit Name
Sz
Bit Name
CHNE
DISEL
DTC Mode Register B (MRB)
Initial
Value
Undefined ⎯
Initial
Value
Undefined ⎯
Undefined ⎯
Undefined ⎯
R/W
R/W
Description
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Description
DTC Chain Transfer Enable
This bit specifies a chain transfer. For details, see
section 8.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of the
end of the specified number of transfers, clearing of the
interrupt source flag, and clearing of DTCER, are not
performed.
0: DTC data transfer completed (waiting for start)
1: DTC data transfer (reads new register information
DTC Interrupt Select
This bit specifies whether CPU interrupt is disabled or
enabled after a data transfer.
0: Interrupt request is issued to the CPU when the
1: The DTC issues interrupt request to the CPU in every
Reserved
These bits have no effect on the DTC operation. The
write value should always be 0.
and transfers data)
specified data transfer is completed. (The DTC clears
the interrupt request flag that causes the activation.)
data transfer. (The DTC does not clear the interrupt
request flag that causes the activation.)
Rev. 6.00 Sep. 24, 2009 Page 171 of 928
Section 8 Data Transfer Controller (DTC)
REJ09B0099-0600

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