DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 193

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.6
The basic bus interface enables direct connection of ROM, SRAM, and so on.
7.6.1
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function. When accessing external address space, it controls
whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used, according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 7.14 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word transfer instruction is performed as two-
byte accesses, and a longword transfer instruction, as four-byte accesses.
16-Bit Access Space: Figure 7.15 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword transfer instruction is performed as two-word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Basic Bus Interface
Figure 7.14 Access Sizes and Data Alignment Control (8-Bit Access Space)
Data Size and Data Alignment
Byte size
Word size
Longword
size
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
D15
Upper data bus
Rev. 6.00 Sep. 24, 2009 Page 145 of 928
D8 D7
Lower data bus
Section 7 Bus Controller
D0
REJ09B0099-0600