DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 755

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(d) FKEY is cleared to H'00 for protection.
(e) The value of the DPFR parameter must be checked and the download result must be
(f) The operating frequency and user branch destination are set to the FPEFEQ and FUBRA
⎯ After the on-chip program storage area is returned to the user-MAT space, the processing
The notes on download are as follows.
⎯ In the download processing, the values of general registers of the CPU are held.
⎯ In the download processing, any interrupts are not accepted. However, NMI interrupt
⎯ When hardware standby mode is entered during download processing, the normal
⎯ Since a stack area of a maximum 128-byte is used, the area must be allocated before setting
⎯ If a flash memory access by the DTC is requested during downloading, the operation
confirmed.
⎯ Check the value of the DPFR parameter (one byte of start address of the download
⎯ If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
⎯ If the value of the DPFR parameter is different from before downloading, check the SS bit
parameters for initialization.
⎯ The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
returns to user procedure program.
requests are held. Therefore, when the user procedure program is returned, the NMI
interrupts occur.
download cannot be guaranteed in the on-chip RAM. Therefore, download must be
executed again.
the SCO bit to 1.
cannot be guaranteed. Therefore, an access request by the DTC must not be generated.
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
and the FK bit in the DPFR parameter to ensure that the download program selection and
FKEY setting were normal, respectively.
ER0).
Rev. 6.00 Sep. 24, 2009 Page 707 of 928
Section 20 Flash Memory
REJ09B0099-0600