DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 441

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6.5
This LSI is not reset internally when TCNT overflows, if the RSTE bit is cleared to 0 in watchdog
timer mode, however TCNT_0 and TCSR_0 of the WDT_0 are reset.
TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this
period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states
after an overflow to write 0 to the WOVF flag.
12.6.6
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF flag may not clear the flag even though the OVF flag has been read while it is 1. If
there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF
flag is polled with the interval timer interrupt disabled, read the OVF flag while it is 1 at least
twice before writing 0 to the OVF flag to clear the flag.
12.6.7
In high-speed or medium-speed mode, after the counter (TCNT) is initialized by clearing TME in
TCSR to 0 while operation is in progress with φSUB (subclock) selected as the dividing clock
(PSS in TCSR set to 1) for the TCNT input clock, TCNT may not initialize properly when TME is
once again set to 1 to activate TCNT operation. To avoid this problem, TCNT by writing a value
of H'00 to it directly.
Internal Reset in Watchdog Timer Mode
OVF Flag Clearing in Interval Timer Mode
Initialization of TCNT by the TME Bit
Rev. 6.00 Sep. 24, 2009 Page 393 of 928
Section 12 Watchdog Timer (WDT)
REJ09B0099-0600