DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 971

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Numerics
11 consecutive recessive bits .................. 637
16-Bit count mode .................................. 369
16-Bit timer pulse unit (TPU)................. 267
8-Bit timers (TMR)................................. 353
A
A/D converter ......................................... 513
A/D converter activation......................... 334
Absolute address....................................... 54
Acknowledge .......................................... 493
Activated by software ............................. 186
Address map ............................................. 72
Address space ........................................... 32
Addressing modes..................................... 52
ADI ......................................................... 527
Analog input channel.............................. 516
Arbitration field ...................................... 649
Arithmetic operations instructions............ 44
Asynchronous mode ............................... 425
B
Bcc............................................................ 49
Bit Manipulation instructions ................... 47
Bit rate ............................................ 418, 640
Bit synchronous circuit ........................... 510
Block data transfer instructions ................ 51
Block transfer mode................................ 183
Boot mode .............................................. 699
Branch instructions ................................... 49
Break....................................................... 467
Break address.................................. 115, 118
Break condition....................................... 117
Buffer operation...................................... 315
Buffer segment ....................................... 640
Bus arbitration ........................................ 165
Bus cycle ................................................ 144
Index
C
CAN bus interface................................... 656
Cascaded connection............................... 369
Cascaded operation ................................. 318
Chain transfer.......................................... 185
Clock pulse generator ............................. 775
Clock synchronous serial format............. 501
Clocked synchronous mode .................... 444
CMIA ...................................................... 370
CMIB ...................................................... 370
Communications protocol ....................... 743
Compare-match count mode ................... 369
Condition field .......................................... 51
Condition-code register............................. 36
Configuration mode ................................ 637
Control field............................................ 645
Controller area network (HCAN)............ 609
Conversion time ...................................... 524
D
D/A converter ......................................... 533
Data direction register (DDR)................. 193
Data field................................................. 645
Data frame............................................... 649
Data register (DR)................................... 193
Data transfer controller ........................... 167
Data transfer instructions .......................... 43
Download pass/fail result parameter....... 686
DTC interface ......................................... 655
DTC vector table..................................... 176
E
Effective address................................. 52, 56
Effective address extension....................... 51
Emulation................................................ 729
ERI.......................................................... 465
Error protection....................................... 727
Rev. 6.00 Sep. 24, 2009 Page 923 of 928
REJ09B0099-0600