DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 448

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once.
RDR cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, or in standby mode, watch mode, or module stop mode.
13.3.3
TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty,
it transfers the transmit data written in TDR to TSR and starts transmission. As TDR and TSR
function as a double buffer in this way, continuous transmit operations are possible. When the SCI
transmits one byte of serial data, if the next transmit data has already been written to TDR, the SCI
transfers the written data to TSR to continue transmission. Although TDR can be read or written to
by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR only
once after confirming that the TDRE bit in SSR is set to 1.
TDR is initialized to H'FF by a reset, or in standby mode, watch mode, or module stop mode.
13.3.4
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be
directly accessed by the CPU.
13.3.5
SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source.
Some bit functions of SMR differ between normal serial communication interface mode and Smart
Card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)
Rev. 6.00 Sep. 24, 2009 Page 400 of 928
REJ09B0099-0600
Bit
7
Bit Name
C/A
Transmit Data Register (TDR)
Transmit Shift Register (TSR)
Serial Mode Register (SMR)
Initial
Value
0
R/W
R/W
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode