DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 162

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
5.6.4
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
5.6.5
When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In
software standby mode and watch mode, the input is accepted asynchronously. For details on the
input conditions, see section 24.4.3, Control Signal Timing.
5.6.6
The NMI interrupt is part of the exception processing performed cooperatively by the LSI’s
internal interrupt controller and the CPU when the system is operating normally under the
specified electrical conditions. No operations, including NMI interrupts, are guaranteed when
operation is not normal (runaway status) due to software problems or abnormal input to the LSI’s
pins. In such cases, the LSI may be restored to the normal program execution state by applying an
external reset.
Rev. 6.00 Sep. 24, 2009 Page 114 of 928
REJ09B0099-0600
L1: EEPMOV.W
Interrupts during Execution of EEPMOV Instruction
IRQ Interrupt
NMI Interrupt Usage Notes
MOV.W
BNE
R4,R4
L1