DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 615

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.10 IEBus Reception Master Address Register 1 (IEMA1)
IEMA1 indicates the lower four bits of the communications destination master unit address in
slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the
contents are changed at the timing of setting the RxS flag in IERSR.
If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is
not in the receive enabled state on control field reception, a receive error interrupt is generated and
the lower 4 bits of the master address are stored in IEMA1. This register cannot be modified.
Bit
7
6
5
4
3 to 0 ⎯
[In master transmission]
Communications frame
Register
[In slave transmission]
Communications frame
Register
Bit Name
IMA3
IMA2
IMA1
IMA0
Figure 17.6 Transmission Signal Format and Registers in Data Transfer
Notes: 1. In slave transmission, the received master address is not saved. If the unit is locked,
Initial Value
0
0
0
0
All 0
Master address
Master address
IEAR1, IEAR2
2. The received slave address is compared with IEAR1 and IEAR2, and if these addresses
3. In slave transmission, the received control bits are not saved. The received control bits
address comparison performed.
match, operation continues.
are decoded to decide the subsequent operation.
(*1)
IEAR1, IEAR2
Slave address
Slave address
IESA1, IESA2
R/W
R
R
R
R
R
(*2)
Description
Lower 4 Bits of IEBus Reception Master Address
Indicates the lower 4 bits of the communications
destination master unit address in slave/broadcast
reception.
Reserved
These bits are always read as 0.
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
CTL3 to CTL0
Control bits
Control bits
in IEMCR
(*3)
Rev. 6.00 Sep. 24, 2009 Page 567 of 928
Message length
Message length
IETBFL
IETBFL
bits
bits
Data bits
Data bits
IETBR
IETBR
REJ09B0099-0600