DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 638

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
3. Set DTCEG5 in the DTC enable register G (DTCERG) to enable the TxRDY interrupt
(3)
Figure 17.8 shows the master transmission flow. Numbers in the following description correspond
to the number in figure 17.8.
1. After the IEB and DTC have been initialized, a master communications request command is
2. When the slave reception has been completed, the CMX flag is cleared, the master
3. The transmit start detection flag (TxS) in IETSR is set when arbitration is won and the master
4. The IEB loads data to be transmitted in the data field from IETBR when the control and
5. Similarly, the data field load and transmission are repeated.
6. The DTC completes the data transfer for the number of specified bytes when data to be
7. A TxRDY interrupt (IETxI) is issued to the CPU when the DTC transfer is completed. In this
8. A transmit normal completion (TxF) interrupt (IETSI) occurs after the last data transfer is
Note: As a transmit status interrupt (IETSI), the transmit error termination (TxE) interrupt as
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REJ09B0099-0600
(IETxI).
Because the TxRDY flag is retained after a reset, the DTC transfer starts when the IETxI is
enabled and the first data for the data field is written to IETBR. The DTC negates the TxRDY
flag and the first byte of DTC transfer is completed.
issued from IECMR. During slave reception, the command execution status flag (CMX) in
IEFLG is set and the master communications request will not be issued.
communications command is executed, and the MRQ flag is set.
address has been transmitted. In this case, one of the transmit status interrupts (IETSI) is
requested to the CPU, and the TxS flag is cleared in the interrupt handling routine.
message length fields have been transmitted and an ACK is received in each field. After that,
the TxRDY flag is set. A DTC transfer request is generated by IETxI and the second byte is
written to the transmit buffer.
transmitted in the last byte is written to. At this time, the DTC does not clear the TxRDY flag.
It, however, clears bit DTCEG5 in the DTC enable register G (DTCERG) so as not to generate
more DTC transfer request.
interrupt handling routine, the TxRDY flag can be cleared. However, since a TxRDY interrupt
will be generated again after the last byte transfer, the TxRDY flag remains set. (Note that the
LUEE bit must be cleared to 0 because an underrun error occurs to terminate the transfer if the
LUEE bit in IECTR is set to 1.) Note, however, that the TxRDY interrupt must be disabled
because the TxRDY interrupt is always generated.
completed. In this case, the CPU clears the TxF flag and completes the normal completion
interrupt and clears the MRQ flag to 0.
Master Transmission Flow
well as the transfer start detection (TxS) and transmit normal completion (TxF) interrupts