DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 171

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI has a built-in bus controller (BSC) that manages the external address space divided into
eight areas. As the bus controller has a bus mastership arbitration function, it controls the
operation of the CPU (the internal bus master) and the data transfer controller (DTC).
7.1
• Manages external address space in area units
• Basic bus interface
• Burst ROM interface
• Idle cycle insertion
• Bus mastership arbitration
• Other features
⎯ Manages the external address space as 8 areas in 2-Mbyte units
⎯ Bus specifications can be set independently for each area
⎯ Burst ROM interface can be set
⎯ H8S/2552 Group, H8S/2506 Group: Chip select signals (CS0 to CS7) can be output for
⎯ H8S/2556 Group: Chip select signals (CS0, CS3 to CS7) can be output for areas 0 and 3 to
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
⎯ Burst ROM interface can be selected for area 0
⎯ One or two states can be selected for the burst cycle
⎯ Idle cycle can be inserted between consecutive read accesses to different external areas
⎯ Idle cycle can be inserted before a write access to an external area immediately after a read
⎯ The on-chip bus arbiter arbitrates the bus mastership among CPU and DTC.
⎯ External bus mastership release function
areas 0 to 7.
7.
access to an external area
Features
Section 7 Bus Controller
Rev. 6.00 Sep. 24, 2009 Page 123 of 928
Section 7 Bus Controller
REJ09B0099-0600