DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 759

IC H8S/2506 MCU FLASH 176-LFBGA

DF2506BR26DV

Manufacturer Part Number
DF2506BR26DV
Description
IC H8S/2506 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2506BR26DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2506BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the
on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, see the RAM map for programming/erasing in figure
20.10.
A single divided block is erased by one erasing processing. For block divisions, see figure 20.4.
To erase two or more blocks, update the erase block number and perform the erasing processing
for each block.
JSR FTDAR setting + 32
Select on-chip program
Start erasing procedure
Set FPEFEQ and
FUBRA parameter
Set SCO to 1 and
to be downloaded
execute download
Set FKEY to H'A5
Clear FKEY to 0
Initialization
FPFR = 0 ?
DPFR = 0?
program
1
Yes
Yes
Initialization error processing
Download error processing
No
No
(a)
Figure 20.12 Erasing Procedure
No
Rev. 6.00 Sep. 24, 2009 Page 711 of 928
JSR FTDAR setting + 16
Disable interrupts and
bus master operation
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
other than CPU
Required block
End erasing
FPFR = 0?
completed?
erasing is
Erasing
1
Yes
Yes
Section 20 Flash Memory
Clear FKEY and erasing
No
error processing
REJ09B0099-0600
(b)
(c)
(d)
(e)
(f)

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