DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 212

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller
Figure 7.30 shows the timing for transition to the bus mastership released state.
7.9.1
When a transition to software standby mode or watch mode is made, external bus mastership
release function is aborted. In the state where MSTPCR is set to H'FFFFFF, and a transition to
sleep mode is made, external bus mastership release function is aborted. When external bus
mastership release function is used in sleep mode, MSTPCR should not be set to H'FFFFFF.
Rev. 6.00 Sep. 24, 2009 Page 164 of 928
REJ09B0099-0600
Address bus
HWR, LWR
Data bus
Usage Note for Bus Mastership Release
Note : n = 0 to 7
[1]
[2]
[3]
[4]
[5]
BREQ
BACK
CSn
RD
AS
The low level of the BREQ pin is sampled at the rise of T
The BACK pin is driven low at one state after the end of CPU read cycle,
releasing bus mastership to external bus master.
The BREQ pin state is still sampled in external bus mastership released state.
The high level of the BREQ pin is sampled.
The BACK pin is driven high, ending the bus mastership release cycles.
Figure 7.30 Bus Mastership Released State Transition Timing
T
0
CPU cycle
T
1
[1]
Minimum
Address
1 state
T
2
[2]
[3]
External bus mastership
released state
2
state.
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
CPU
cycle
[5]