DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 646

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
9. When the last data is received, a receive normal completion (RxF) interrupt (IERSI) occurs. In
Notes: 1. As a receive status interrupt (IERSI), an receive error completion (RxE) interrupt as
Rev. 6.00 Sep. 24, 2009 Page 598 of 928
REJ09B0099-0600
this case, the CPU clears the RxF flag to complete the receive normal completion interrupt.
The MRQ flag is cleared to 0.
2. The interrupt occurs after the DTC transfer has been completed. Accordingly, the
Interrupt
IERxI (RxRDY)
(TO DTC)
IERxI (RxRDY)
(TO CPU)
IERSI
(TO CPU)
IECMR
IECTR
IERSR
IEFLG
RxRDY
well as the receive start detection (RxS) and receive normal completion (RxF)
interrupts must be enabled. If a receive error completion interrupt is disabled, no
interrupt is generated even if the reception is terminated by an error.
interrupt described in item 8 actually occurs after item 9 above.
MRQ
CMX
SRQ
SRE
RxS
RxF
RE
Slave reception
H: Header, MA: Master address field, SA: Slave address field,
CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field
(1)
Master reception request
Figure 17.11 Master Receive Operation Timing
Dn
(2)
(2)
H
MA
SA
CF
(3)
Master reception
LF
(4)
(4)
DTC transfer
of 1st byte
D1
(5)
(5)
D2
of (n-2)th byte
DTC transfer
(6)
(6)
Dn-1
of (n-1)th byte
DTC transfer
Dn
(9)
(7)
(7)
(9)
(8)
DTC transfer
(9)
of nth byte