HD64F3644H Renesas Electronics America, HD64F3644H Datasheet

IC H8 MCU FLASH 32K 64-QFP

HD64F3644H

Manufacturer Part Number
HD64F3644H
Description
IC H8 MCU FLASH 32K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644H

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website:
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Renesas Electronics Corporation
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, 2010

Related parts for HD64F3644H

HD64F3644H Summary of contents

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

Page 2

All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

Page 3

H8/3644 Group, H8/3644R Group H8/3644 F-ZTAT 8 H8/3642A F-ZTAT Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series H8/3644 H8/3643 H8/3642 H8/3641 H8/3640 The revision list can be viewed directly by clicking the title page. The revision list summarizes the ...

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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...

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Rev. 6.00 Sep 12, 2006 page ...

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The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3644 Group has a system-on-a-chip architecture that includes ...

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Rev. 6.00 Sep 12, 2006 page ...

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Main Revisions in This Edition Item Page All — 3.3.2 Interrupt Control 64 Registers Interrupt Edge Select Register 2 (IEGR2) 6.2.2 Memory Map 102, 103 Description of socket adapter deleted Table 6.2 Socket Adapter Figure 6.2 Socket Adapter Pin Correspondence ...

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Item Page 10.2.2 Register 281 Descriptions Serial Control/Status Register 1 (SCSR1) 10.3.1 Overview 291 Figure 10.6 SCI3 Block Diagram 10.3.7 Interrupts 336 Table 10.16 SCI3 Interrupt Requests Rev. 6.00 Sep 12, 2006 page viii of xx Revision (See Manual for ...

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Item Page 13.2.4 DC 374 Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) Table 13.6 DC Characteristics 13.2.5 AC 380 Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) Table 13.9 Serial Interface (SCI3) Timing 13.3.5 AC 404 Characteristics (HD6433644R, HD6433643R, HD6433642R, HD6433641R, HD6433640R) Table ...

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Item Page A.1 Instructions 427 Table A.1 Instruction Set B.2 Functions 485 IEGR2—Interrupt edge select register 2 Rev. 6.00 Sep 12, 2006 page Revision (See Manual for Details) Table amended Mnemonic Operation PUSH Rs W SP–2 SP ...

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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Internal Block Diagram..................................................................................................... 1.3 Pin Arrangement and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 10 Section 2 CPU ...................................................................................................................... 15 2.1 Overview........................................................................................................................... 15 2.1.1 Features................................................................................................................ 15 2.1.2 Address Space...................................................................................................... 16 ...

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Exception-Handling State .................................................................................... 48 2.8 Memory Map..................................................................................................................... 49 2.9 Application Notes ............................................................................................................. 50 2.9.1 Notes on Data Access .......................................................................................... 50 2.9.2 Notes on Bit Manipulation ................................................................................... 52 2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 58 Section 3 ...

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Transition to Standby Mode................................................................................. 95 5.3.2 Clearing Standby Mode........................................................................................ 95 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared ..................................... 96 5.4 Watch Mode...................................................................................................................... 96 5.4.1 Transition to Watch Mode ................................................................................... 96 5.4.2 Clearing Watch Mode .......................................................................................... 97 5.4.3 ...

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On-Board Programming Modes ........................................................................................ 120 6.6.1 Boot Mode ........................................................................................................... 120 6.6.2 User Program Mode............................................................................................. 125 6.7 Programming and Erasing Flash Memory......................................................................... 127 6.7.1 Program Mode ..................................................................................................... 127 6.7.2 Program-Verify Mode.......................................................................................... 128 6.7.3 Programming Flowchart and Sample Program..................................................... 129 6.7.4 ...

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MOS Input Pull-Up.............................................................................................. 185 8.5 Port 5................................................................................................................................. 186 8.5.1 Overview.............................................................................................................. 186 8.5.2 Register Configuration and Description............................................................... 186 8.5.3 Pin Functions ....................................................................................................... 188 8.5.4 Pin States.............................................................................................................. 189 8.5.5 MOS Input Pull-Up.............................................................................................. 189 8.6 Port 6................................................................................................................................. 190 8.6.1 Overview.............................................................................................................. 190 8.6.2 ...

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Overview.............................................................................................................. 209 9.3.2 Register Descriptions ........................................................................................... 211 9.3.3 Timer Operation................................................................................................... 213 9.3.4 Timer B1 Operation States................................................................................... 214 9.4 Timer V............................................................................................................................. 215 9.4.1 Overview.............................................................................................................. 215 9.4.2 Register Descriptions ........................................................................................... 218 9.4.3 Timer Operation................................................................................................... 224 9.4.4 Timer V Operation Modes ................................................................................... ...

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Multiprocessor Communication Function ............................................................ 329 10.3.7 Interrupts.............................................................................................................. 336 10.3.8 Application Notes ................................................................................................ 337 Section 11 14-Bit PWM 11.1 Overview........................................................................................................................... 341 11.1.1 Features................................................................................................................ 341 11.1.2 Block Diagram ..................................................................................................... 341 11.1.3 Pin Configuration................................................................................................. 342 11.1.4 Register Configuration ......................................................................................... 342 11.2 Register ...

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AC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) ........................................................................................................ 376 13.2.6 A/D Converter Characteristics ............................................................................. 381 13.3 Electrical Characteristics (ZTAT and R of the Mask ROM Version) ............................... 382 13.3.1 Power Supply Voltage and Operating Range ....................................................... 382 13.3.2 DC ...

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Appendix E Product Code Lineup Appendix F Package Dimensions .................................................................................. 522 ................................................................................... 524 Rev. 6.00 Sep 12, 2006 page xix of xx ...

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Rev. 6.00 Sep 12, 2006 page ...

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Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3644 Group of microcomputers are equipped with a ...

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Section 1 Overview Table 1.1 Features Item Description CPU High-speed H8/300L CPU General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed Max. operation speed: 5 MHz (mask ROM and ZTAT versions) Add/subtract: 0.4 ...

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Item Description Power-down Seven power-down modes modes Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode Memory Large on-chip memory H8/3644: 32-kbyte ROM, 1-kbyte RAM H8/3643: 24-kbyte ROM, 1-kbyte RAM H8/3642: 16-kbyte ...

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Section 1 Overview Item Description Timers Timer X: 16-bit timer Count-up timer with selection of three internal clock signals or event input from external pin Output compare (2 output pins) Input capture (4 input pins) Watchdog timer Reset signal generated ...

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... HD6433640P HD6433640RP HD6433640W HD6433640RW Notes: 1. Applies only to F-ZTAT the ZTAT, and R of the mask ROM version for the definition of Product Code ZTAT™ F-ZTAT™ Version Version HD6473644H HD64F3644H HD6473644RH HD6473644P HD64F3644P HD6473644RP HD6473644W HD64F3644W HD6473644RW HD64F3643H HD64F3643P HD64F3643W HD64F3642AH HD64F3642AP ...

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Section 1 Overview 1.2 Internal Block Diagram Figure 1.1 shows a block diagram of the H8/3644 Group. P1 /TMOW 0 P1 /PWM 4 P1 /IRQ /IRQ /IRQ /TRGV /SCK 0 3 ...

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Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3644 Group pin arrangement is shown in figures 1.2 (FP-64A), 1.3 (DP-64S), and 1.4 (TFP-80C). P2 /TXD / / /SCK ...

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Section 1 Overview P1 /IRQ /TRGV / / / / / /AN 8 ...

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/TXD / / /SCK /TMOW /PWM /IRQ /IRQ 70 6 ...

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Section 1 Overview 1.3.2 Pin Functions Table 1.2 outlines the pin functions of the H8/3644 Group. Table 1.2 Pin Functions Type Symbol FP-64A Power source pins Clock pins ...

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Type Symbol FP-64A IRQ Interrupt 16 0 IRQ pins 55 1 IRQ 56 2 IRQ 57 3 INT INT 0 Timer pins TMOW 53 TMIB 31 TMOV 37 TMCIV ...

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Section 1 Overview Type Symbol FP-64A Timer pins FTIA 42 FTIB 43 FTIC 44 FTID 45 14-bit PWM 54 PWM pin I/O ports 64 ...

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Type Symbol FP-64A I/O ports 54 ...

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Section 1 Overview Type Symbol FP-64A Flash memory Other NC Rev. 6.00 Sep 12, 2006 page 14 of 526 REJ09B0326-0600 Pin No. DP-64S TFP-80C I Input 1, 16, 20, 21, 30, 39, 40, 41, 48, ...

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Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. General-register architecture ...

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Section 2 CPU Low-power operation modes SLEEP instruction for transfer to low-power operation 2.1.2 Address Space The H8/300L CPU supports an address space kbytes for storing program code and data. See section 2.8, Memory Map, for ...

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General registers (Rn R0H R1H R2H R3H R4H R5H R6H R7H (SP) Control registers (CR CCR Figure 2.1 CPU Registers 0 R0L R1L R2L ...

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Section 2 CPU 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the ...

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Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using ...

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Section 2 CPU Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 2.2.3 Initial Register Values In reset exception handling, the program counter (PC) is initialized by a vector address (H'0000) load, ...

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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte data RnH MSB ...

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Section 2 CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. When word data beginning at an odd ...

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Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Address Modes 1 Register direct 2 Register indirect ...

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Section 2 CPU Register indirect with pre-decrement @–Rn The @–Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented ...

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Effective Address Calculation Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use ...

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Section 2 CPU Table 2.2 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register indirect Register indirect, @ Register indirect ...

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Addressing Mode and No. Instruction Format 5 Absolute address @aa abs @aa: abs 6 Immediate #xx IMM #xx: IMM 7 Program-counter relative @(d:8, PC ...

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Section 2 CPU Addressing Mode and No. Instruction Format 8 Memory indirect, @@aa abs Legend: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Rev. 6.00 Sep 12, 2006 page ...

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Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions MOV, PUSH * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ...

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Section 2 CPU Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), <Ead> Destination operand (EAs), <Eas> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V ...

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Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Size * Instruction Function MOV B/W (EAs) Moves data between two general registers or between a general ...

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Section 2 CPU Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 ...

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Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Size * Instruction Function ADD B/W Rd ± Rs SUB Performs addition or subtraction on data in two general registers, or addition on immediate data and data ...

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Section 2 CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Size * Instruction Function AND B Rd Performs a logical AND operation on a general register and another general ...

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Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions Legend: op: Operation field rm, rn: Register field IMM: Immediate data ...

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Section 2 CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Size * Instruction Function BSET B 1 Sets a specified bit in a general register or memory ...

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Size * Instruction Function BXOR B C XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIXOR B C XORs the C flag with the inverse of ...

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Section 2 CPU Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate ...

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Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont IMM ...

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Section 2 CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Size * Instruction Function Bcc Branches to the designated address if condition cc is true. The branching ...

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Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes 8 7 disp 8 ...

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Section 2 CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Size * Instruction Function RTE Returns from an exception-handling routine SLEEP Causes a transition ...

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Legend: op: Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code ...

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Section 2 CPU 15 Legend: op: Operation field Figure 2.10 Block Data Transfer Instruction Code 2.6 Basic Operational Timing CPU operation is synchronized by a system clock ( ) or a subclock ( clock signals see section 4, Clock Pulse ...

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Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions ...

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Section 2 CPU Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in the case of three-state access to an on-chip peripheral module SUB Internal address bus Internal read signal Internal data bus (read access) ...

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CPU state Reset state The CPU is initialized Program execution state Program halt state A state in which some or all of the chip functions are stopped to conserve power Exception- handling state A transient state in which the CPU ...

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Section 2 CPU Reset state Reset occurs Program halt state 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium ...

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Memory Map Figure 2.16 shows a memory map of the H8/3644 Group. H'0000 Interrupt vectors H'002F H'0030 H'1FFF H'2FFF H'3FFF On-chip ROM H'5FFF H'7FFF Reserved H'F770 Internal I/O registers (16 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FF7F H'FF80 H'FF7F ...

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Section 2 CPU 2.9 Application Notes 2.9.1 Notes on Data Access 1. Access to empty areas The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If ...

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H'0000 Interrupt vector area (48 bytes) H'002F H'0030 On-chip ROM H'7FFF Reserved H'F770 Internal I/O registers (16 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FF7F H'FF80 Reserved H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Notes: The H8/3644 is shown as ...

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Section 2 CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases ...

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Example 2: BSET instruction executed designating port 3 P3 and P3 are designated as input pins, with a low-level signal input signal The remaining pins example, the BSET instruction is used ...

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Section 2 CPU As a result of this operation, bit 0 in PDR3 becomes 1, and P3 However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data ...

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Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above high-level signal The remaining pins signals. In this ...

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Section 2 CPU As a result of this operation, bit 0 in PCR3 becomes 0, making P3 and 6 in PCR3 change that P3 To avoid this problem, store a copy of the PCR3 data in a ...

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Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers that contain write-only bits. Table 2.12 Registers with Shared Addresses Register Name Output compare register AH and output compare register BH (timer X) OCRAH/OCRBH ...

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Section 2 CPU 2.9.3 Notes on Use of the EEPMOV Instruction The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by ...

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Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3644 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority ...

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Section 3 Exception Handling Reset exception handling takes place as follows. The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. The PC is ...

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Reset by Watchdog Timer: The watchdog timer counter (TCW) starts counting up when the WDON bit is set the watchdog timer control/status register (TCSRW). If TCW overflows, the WRST bit is set TCSRW and ...

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Section 3 Exception Handling Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt RES Reset IRQ IRQ 0 0 IRQ IRQ 1 1 IRQ IRQ 2 2 IRQ IRQ 3 3 INT INT 0 0 INT INT 1 1 ...

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Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Interrupt edge select register 1 Interrupt edge select register 2 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 ...

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Section 3 Exception Handling Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ Bit 2 IRQ 2 Bit 2: IEG2 Description Falling edge of IRQ 0 Rising edge of IRQ 1 Edge Select (IEG1): Bit 1 selects ...

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Edge Select (INTEG6): Bit 6 selects the input sensing of the INT Bit 6 INT 6 pin. Bit 6: INTEG6 Description Falling edge of INT 0 Rising edge of INT 1 Edge Select (INTEG5): Bit 5 selects the input sensing ...

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Section 3 Exception Handling Bit 6 Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt requests. Bit 6: IENTA Description 0 Disables timer A interrupt requests 1 Enables timer A interrupt requests Bit 5 Reserved ...

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Bit 6 A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter interrupt requests. Bit 6: IENAD Description 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Bit 5 Reserved Bit: Bit 5 is reserved: ...

Page 90

Section 3 Exception Handling Interrupt Request Register 1 (IRR1) Bit 7 IRRTB1 IRRTA Initial value 0 R/W * R/W * Read/Write Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register, in ...

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Bits IRQ to IRQ Interrupt Request Flags (IRRI3 to IRRI0 Bit n: IRRIn Description 0 Clearing condition: When IRRIn = cleared by writing 0 1 Setting condition: When pin IRQ is input ...

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Section 3 Exception Handling Bit 5 Reserved bit: Bit 5 is reserved always read as 0 and cannot be modified. Bit 4 SCI1 Interrupt Request Flag (IRRS1) Bit 4: IRRS1 Description 0 Clearing condition: When IRRS1 = 1, ...

Page 93

External Interrupts There are 12 external interrupts: IRQ Interrupts IRQ to IRQ : Interrupts IRQ 3 0 IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, 0 depending on the settings of bits ...

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Section 3 Exception Handling 3.3.4 Internal Interrupts There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition ...

Page 95

Interrupt operation is described as follows interrupt occurs while the interrupt enable register bit is set interrupt request signal is sent to the interrupt controller. When the interrupt controller receives an interrupt request, it sets ...

Page 96

Section 3 Exception Handling Program execution state IRRI0 = 1 Yes IEN0 = 1 Yes Yes PC contents saved CCR contents saved I 1 Branch to interrupt handling routine Legend: PC: Program counter CCR: Condition code register ...

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SP – – – – (R7) Stack area Prior to start of interrupt exception handling Legend Upper 8 bits of program counter (PC Lower 8 bits of ...

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Section 3 Exception Handling Rev. 6.00 Sep 12, 2006 page 76 of 526 REJ09B0326-0600 Figure 3.5 Interrupt Sequence ...

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Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item Waiting time for completion of ...

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Section 3 Exception Handling 3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3644 Group, the least significant bit of the address is regarded as 0. Access to the stack always takes place ...

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Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port ...

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Section 3 Exception Handling CCR I bit 1 Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 CCR I bit 0 Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Rev. 6.00 Sep 12, ...

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Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator ...

Page 104

Section 4 Clock Pulse Generators 4.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator providing external clock input. Connecting a Crystal Resonator: Figure 4.2 shows ...

Page 105

Connecting a Ceramic Resonator: Figure 4.4 shows a typical method of connecting a ceramic resonator. OSC 1 OSC 2 Figure 4.4 Typical Connection to Ceramic Resonator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic ...

Page 106

Section 4 Clock Pulse Generators External Clock Input Method: Connect an external clock signal to pin OSC OSC open. Figure 4.6 shows a typical connection. 2 OSC 1 OSC 2 Figure 4.6 External Clock Input (Example) Frequency Oscillator Clock ( ...

Page 107

Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal resonator Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Resonator Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X V and ...

Page 108

Section 4 Clock Pulse Generators In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output ...

Page 109

Section 5 Power-Down Modes 5.1 Overview The H8/3644 Group has eight modes of operation after a reset. These include seven power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the eight operating modes. Table ...

Page 110

Section 5 Power-Down Modes Reset state Program halt state Standby mode *4 *1 instruction Watch mode Mode Transition Conditions (1) LSON MSON SSBY ...

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Table 5.2 Internal State in Each Operating Mode Active Mode High- Function Speed System clock oscillator Functions Subclock oscillator Functions CPU Instructions Functions operations Registers RAM I/O ports External IRQ Functions 0 interrupts IRQ 1 IRQ 2 IRQ 3 INT ...

Page 112

Section 5 Power-Down Modes 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Registers Name System control register 1 System control register 2 System Control Register 1 ...

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Bits Standby Timer Select (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due ...

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Section 5 Power-Down Modes System Control Register 2 (SYSCR2) Bit 7 Initial value 1 Read/Write SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits Reserved Bits: These bits ...

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Bit 3 Direct Transfer on Flag (DTON): This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after ...

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Section 5 Power-Down Modes Bits 1 and 0 Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock rate ( /2, /4, or /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. W ...

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Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode Operation in sleep (medium-speed) mode is clocked at the frequency designated ...

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Section 5 Power-Down Modes 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. When a crystal oscillator is used The table 5.4 gives settings for various operating frequencies. Set ...

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Clearing Watch Mode Watch mode is cleared by an interrupt (timer A or IRQ Clearing by interrupt When watch mode is cleared by a timer A interrupt or IRQ transition is made depends on the settings of LSON in ...

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Section 5 Power-Down Modes 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, IRQ RES pin. Clearing by interrupt When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is ...

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Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are /2, /4, and / 5.7 Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) ...

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Section 5 Power-Down Modes 5.8 Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. ...

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Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit ...

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Section 5 Power-Down Modes Rev. 6.00 Sep 12, 2006 page 102 of 526 REJ09B0326-0600 ...

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Overview The H8/3644 has 32 kbytes of on-chip mask ROM, PROM or flash memory. The H8/3643 has 24 kbytes of mask ROM or flash memory. The H8/3642 has 16 kbytes of mask ROM or flash memory. The H8/3641 has ...

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Section 6 ROM 6.2 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as ...

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Programming The H8/3644 write, verify, and other modes are selected as shown in table 6.2 in PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/3644 Mode Write L H Verify ...

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Section 6 ROM 6.3.1 Writing and Verifying An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. ...

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Table 6.3 and table 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics (Conditions 6.0 V ±0. Item Input high OE, CE level voltage Input ...

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Section 6 ROM Table 6.4 AC Characteristics (Conditions 6.0 V ±0. Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP ...

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Figure 6.4 shows a PROM write/verify timing diagram. Address t AS Data Input data VPS VCS OPW Note ...

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Section 6 ROM Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. 6.3.3 Reliability of Programmed Data A highly effective way to improve data retention characteristics is to bake the programmed ...

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Flash Memory Overview 6.4.1 Principle of Flash Memory Operation Table 6.5 illustrates the principle of operation of the on-chip flash memory in the H8/3644F, H8/3643F, and H8/3642AF. Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage ...

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Section 6 ROM 6.4.2 Mode Pin Settings and ROM Space The H8/3644F has 32 kbytes of on-chip flash memory, the H8/3643F has 24 kbytes, and the H8/3642AF has 16 kbytes. The ROM is connected to the CPU by a 16-bit ...

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Block Diagram Figure 6.6 shows a block diagram of the flash memory FLMCR EBR1 EBR2 Legend: FLMCR: Flash memory control register EBR1: Erase block register 1 EBR2: Erase block register 2 Figure 6.6 Block Diagram of Flash ...

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Section 6 ROM 6.4.5 Pin Configuration The flash memory is controlled by means of the pins shown in table 6.6. Table 6.6 Flash Memory Pins Pin Name Abbreviation Programming power FV PP Mode pin TEST Transmit data TXD Receive data ...

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Flash Memory Register Descriptions 6.5.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in ...

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Section 6 ROM Bit 2 Program-Verify Mode (PV Bit 2 selects transition to or exit from program-verify mode. Bit 2: PV Description 0 Exit from program-verify mode 1 Transition to program-verify mode Note not set multiple ...

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Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure. EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 ...

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Section 6 ROM 6.5.3 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies small flash-memory blocks for programming or erasure. EBR2 is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, ...

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Small block area (4 kbytes) Large block area (H8/3644F: 28 kbytes) (H8/3643F: 20 kbytes) Table 6.8 Correspondence between Erase Blocks and EBR1/EBR2 Bits Register Bit EBR1 Register Bit EBR2 ...

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Section 6 ROM 6.6 On-Board Programming Modes When an on-board programming mode is selected, on-chip flash memory programming, erasing, and verifying can be carried out. There are two on-board programming modes boot mode and user program mode set by the ...

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Boot Mode Execution Procedure: The boot mode execution procedure is shown below. Start Set pins to boot mode for chip 1 and execute reset-start Host transmits H'00 data continuously 2 at prescribed bit rate Chip measures low period of H'00 ...

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Section 6 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8/3644F, H8/3643F, or H8/3642AF measures the low period of the asynchronous SCI communication data transmitted continuously from the host (figure 6.10). The data format should be ...

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Table 6.10 System Clock Oscillation Frequencies Permitting Automatic Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate System Clock Oscillation Frequencies (f Host Bit Rate * Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate 9600 bps 8 MHz to 16 MHz ...

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Section 6 ROM Notes on Use of Boot Mode: 1. When the chip (H8/3644F, H8/3643F, or H8/3642AF) comes out of reset in boot mode, it measures the low period of the input at the SCI3’s RXD pin. The reset should ...

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Boot mode can be exited by driving the reset pin low, then releasing 12 V application to the TEST pin and FV pin at least 10 system clock cycles later, and setting the TEST pin release the ...

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Section 6 ROM User Program Mode Execution Procedure * RAM is shown below. 1 Reset-start (TEST = V Branch to flash memory on-board 2 reprogramming program Transfer flash memory 3 reprogramming routine to RAM Branch to flash memory 4 reprogramming ...

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Programming and Erasing Flash Memory The on-chip flash memory of the H8/3644F, H8/3643F, and H8/3642AF is programmed and erased by software, using the CPU. There are five flash memory operating modes: program mode, erase mode, program-verify mode, erase-verify mode, ...

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Section 6 ROM 6.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the programming time, exit programming mode (clear ...

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Programming Flowchart and Sample Program Flowchart for Programming One Byte Start Set erase block register (set bit for block to be programmed to 1) Write data to flash memory (flash memory latches write address *1 and data ...

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Section 6 ROM Sample Program for Programming One Byte This program uses the following registers: R0H: Used for erase block specification. R1H: Stores programming data. R1L: Stores read data. R3: Stores the programming address. Valid address specifications are H'0000 to ...

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BSET #0, LOOP1: SUBS #1, MOV.W R4, BNE LOOP1 BCLR #0, MOV.B #H'50, MOV.B R4L, MOV.B #H'b, R4H BSET #2, LOOP2: DEC R4H BNE LOOP2 MOV.B @R3, CMP.B R1H, BEQ PVOK BCLR #2, @FLMCR:8 CMP.B #H'06, BEQ NGEND ADD.W R5, ...

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Section 6 ROM 6.7.4 Erase Mode To erase the flash memory, follow the erasing algorithm shown in figure 6.14. This erasing algorithm enables data to be erased without subjecting the device to voltage stress or impairing the reliability of the ...

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Erase Flowcharts and Sample Programs Flowchart for Erasing One Block Start Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite Enable watchdog ...

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Section 6 ROM Prewrite Flowchart Start Set erase block register (set bit for block to be programmed Set start address Write H'00 to flash memory (flash memory latches programmed address *1 and data) *2 ...

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Sample Program for Erasing One Block This program uses the following registers: R0: Used for erase block specification. Also stores address used in prewrite and erase-verify. R1H: Stores read data. Also used in dummy write. R2: Stores last address of ...

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Section 6 ROM PREWRT: MOV.B #H'00, MOV.W #H'a, PREWRS: INC R6L MOV.B #H'00, MOV.B R1H, MOV.W #H'FE5A, R4 MOV.B R4L, MOV.B R4H, MOV.B #H'36, MOV.B R4L, MOV.W R5, BSET #0, LOOPR1: SUBS #1, MOV.W R4, BNE LOOPR1 BCLR #0, MOV.B ...

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ERASES: MOV.W #H'0000, R6 MOV.W #H'd, ERASE: ADDS #1, MOV.W #H'e5A, R4 MOV.B R4L, MOV.B R4H, MOV.B #H'36, MOV.B R4L, MOV.W R5, BSET #1, LOOPE: NOP NOP NOP NOP SUBS #1, MOV.W R4, BNE LOOPE BCLR #1, MOV.B #H'50, MOV.B ...

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Section 6 ROM CMP.W R2, BNE EVR2 BRA OKEND RERASE: BCLR #3, SUBS #1, MOV.W #H'0004, R4 CMP.W R4, BPL BRER ADD.W R5, BRER: MOV.W #H'025A, R4 CMP.W R4, BNE ERASE BRA ABEND2 OKEND: BCLR #3, MOV.B #H'00, MOV.B R6L, ...

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Flowchart for Erasing Multiple Blocks Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite) Enable watchdog timer Select erase mode (E bit = 1 in FLMCR) ...

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Section 6 ROM Sample Program for Erasing Multiple Blocks This program uses the following registers: R0: Used for erase block specification (set as explained below). Also stores address used in prewrite and erase-verify. R1H: Used to test bits 8 to ...

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Notes this sample program, the stack pointer (SP) is set to address H'FF80. On-chip RAM addresses H'FF7E and H'FF7F are used as a stack area. Therefore addresses H'FF7E and H'FF7F should not be used when this program is ...

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Section 6 ROM MOV.W @R2+, BRA PRETST ; Execute prewrite PREWRT: MOV.W @R2+, PREW: MOV.B #H'00, MOV.W #H'a, PREWRS: INC R6L MOV.B #H'00 MOV.B R1H, MOV.W #H'FE5A, MOV.B R4L, MOV.B R4H, MOV.B #H'36, MOV.B R4L, MOV.W R5, BSET #0, LOOPR1: ...

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MOV.W #H'e5A, MOV.B R4L, MOV.B R4H, MOV.B #H'36, MOV.B R4L, MOV.W R5, BSET #1, LOOPE: NOP NOP NOP NOP SUBS #1, MOV.W R4, BNE LOOPE BCLR #1, MOV.B #H'50, MOV.B R4L, Execute erase-verify ; EVR: MOV.W #RAMSTR, R2 MOV.W #ERVADR, ...

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Section 6 ROM EVR2: MOV.B #H'FF, MOV.B R1H, MOV.B #H'c, LOOPEP: DEC R4H BNE LOOPEP MOV.B @R3+, CMP.B #H'FF, BNE BLKAD MOV.W @R2, CMP.W R4, BNE EVR2 CMP.B #H'08, BMI SBCLR MOV.B R1L, SUBX #H'08, BCLR R1H, BRA BLKAD SBCLR: ...

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EOWARI: ABEND2: Loop Counter and Watchdog Timer Overflow Interval Settings in Programs: The settings of #a, #b, #c, #d, and #e in the program examples depend on the clock frequency. Sample loop counter settings for typical ...

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Section 6 ROM Table 6.11 Set Values of #a, #b, #c, and #d for Typical Operating Frequencies when Sample Program Is Executed in On-Chip Memory (RAM) Meaning of Variable Set Time Programming time 15.8 µs (initial set ...

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Examples: Sample calculations when executing a program in on-chip memory (RAM operating frequency of 6 MHz 10 ...

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Section 6 ROM 6.7.8 Protect Modes There are two modes for flash memory program/erase protection: hardware protection and software protection. These two protection modes are described below. Software Protection: With software protection, setting the bit in the ...

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Hardware Protection: Hardware protection refers to a state in which programming/erasing of flash memory is forcibly suspended or disabled. At this time, the flash memory control register (FLMCR) and erase block register (EBR1 and EBR2) settings are cleared. Details of ...

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Section 6 ROM 6.8 Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF) 6.8.1 PROM Mode Setting The H8/3644F, H8/3643F, and H8/3642AF, in which the on-chip ROM is flash memory, have a PROM mode as well as the on-board programming modes ...

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Operation in PROM Mode The program/erase/verify specifications in PROM mode are the same as for the standard HN28F101 flash memory. The H8/3644F, H8/3643F, and H8/3642AF do not have a device recognition code, so the programmer cannot read the device ...

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Section 6 ROM Table 6.14 PROM Mode Commands Command Cycles Memory read 1 Erase setup/erase 2 Erase-verify 2 Auto-erase setup/ 2 auto-erase Program setup/ 2 program Program-verify 2 Reset 2 Legend: PA: Program address EA: Erase-verify address RA: Read address ...

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High-Speed, High-Reliability Programming: Unused areas of the flash memory in the H8/3644F, H8/3643F, or H8/3642AF contain H'FF data (initial value). The flash memory uses a high-speed, high-reliability programming procedure. This procedure provides higher programming speed without subjecting the device to ...

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Section 6 ROM High-Speed, High-Reliability Erasing: The flash memory in the H8/3644F, H8/3643F, and H8/3642AF uses a high-speed, high-reliability erasing procedure. This procedure provides higher erasing speed without subjecting the device to voltage stress and without sacrificing the reliability of ...

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Table 6.15 DC Characteristics in PROM Mode (Conditions 5.0 V ±10 Item Input high OE, CE, WE voltage Input low ...

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Section 6 ROM Table 6.16 AC Characteristics in PROM Mode (Conditions 5.0 V ±10 Item Command write cycle Address setup time Address hold time Data setup time Data hold time CE setup time CE hold time ...

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Auto-erase setup 5 VPS 5.0 V Address CE t CES WEP OEWS t CEH Command I/O7 input Command I/O0 to I/O6 input Figure 6.20 Auto-Erase Timing ...

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Section 6 ROM Program setup 5 5 VPS Address CE t CES OE t CWC t WEP t t CES t CEH OEWS WE t WEH I/O7 ...

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Erase setup 5 VPS 5.0 V Address OEWS t t WEP CES WE t CEH I/O0 to I/O7 Command input Note: Erase -verify data ...

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Section 6 ROM 6.9 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming modes and PROM mode are summarized below. 1. Program with the specified voltages and timing. The rated programming voltage (V If the PROM ...

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Oscillation must have stabilized (following the elapse of the oscillation settling time stopped. power is turned on, hold the RES pin low for the duration of the When the V CC oscillation settling time * The MCU must ...

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Section 6 ROM t OSC1 3 (boot mode (user program mode) ...

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Design a current margin into the programming voltage (V Insure that V remains within the range 12.0 V ±0.6 V (11 12.6 V) during PP programming and erasing. Programming and erasing may become impossible outside this range. ...

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Section 6 ROM the status of this bit. A byte data comparison is necessary to check whether 12V is being applied. The relevant coding is shown below. LABEL1: MOV.B CMP.B BEQ Sample program for detection of 12 ...

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Table 6.18 Flash Memory AC Characteristics 12.0 V ±0 –20°C to +75°C (regular specifications Item ...

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Section 6 ROM Rev. 6.00 Sep 12, 2006 page 166 of 526 REJ09B0326-0600 ...

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Overview The H8/3644 Group has 1 kbyte and 512 byte of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 ...

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Section 7 RAM Rev. 6.00 Sep 12, 2006 page 168 of 526 REJ09B0326-0600 ...

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Overview The H8/3644 Group is provided with three 8-bit I/O ports, three 5-bit I/O ports, two 3-bit I/O ports, and one 8-bit input-only port. Table 8.1 indicates the functions of each port. Each port has of a port control ...

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Section 8 I/O Ports Port Description Port 6 8-bit I/O port High-current port Port 7 5-bit I/O port Port 8 8-bit I/O port Port 9 5-bit I/O port Port B 8-bit input port Note: * There function ...

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Port 1 8.2.1 Overview Port 5-bit I/O port. Figure 8.1 shows its pin configuration. Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port ...

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Section 8 I/O Ports PDR1 is an 8-bit register that stores data for port 1 pins P1 while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 ...

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Port Mode Register 1 (PMR1) Bit 7 IRQ3 IRQ2 Initial value 0 Read/Write R/W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'04. IRQ IRQ IRQ ...

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Section 8 I/O Ports Bit 4 P1 /PWM Pin Function Switch (PWM): This bit selects whether pin PWM. 4 Bit 4: PWM Description 0 Functions Functions as PWM output pin Bit ...

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Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Pin Functions and Selection Method P1 /IRQ /TRGV The pin function depends on bit IRQ3 in PMR1 and bit PCR1 7 3 ...

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Section 8 I/O Ports 8.2.4 Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset P1 /IRQ /TRGV High impedance P1 /IRQ /IRQ ...

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Port 2 8.3.1 Overview Port 3-bit I/O port, configured as shown in figure 8.2. Figure 8.2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration. Table 8.5 Port ...

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Section 8 I/O Ports Port Control Register 2 (PCR2) Bit 7 Initial value 0 Read/Write PCR2 is an 8-bit register for controlling whether each of the port 1 pins P2 input pin or output pin. Setting a PCR2 bit to ...

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