HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 282
HD64F3644H
Manufacturer Part Number
HD64F3644H
Description
IC H8 MCU FLASH 32K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644H
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 9 Timers
Rev. 6.00 Sep 12, 2006 page 260 of 526
REJ09B0326-0600
FTIA
Input capture
signal
FRC
ICRA
ICRC
Buffered input capture timing
Input capture can be buffered by using ICRC or ICRD as a buffer for ICRA or ICRB.
Figure 9.26 shows the timing when ICRA is buffered by ICRC (BUFEA = 1) and both
the rising and falling edges are selected (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and
IEDGC = 1).
When ICRC or ICRD is used as a buffer register, the input capture flag is still set by the
selected edge of the input capture input signal. For example, if ICRC is used to buffer ICRA,
when the edge transition selected by the IEDGC bit occurs at the input capture pin, ICFC will
be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however.
In buffered operation, if the upper byte of one of the two registers that receives a data transfer
(ICRA and ICRC, or ICRB and ICRD) is being read when an input capture signal would
normally occur, the input capture signal will be delayed by one system clock ( ). Figure 9.27
shows the case when BUFEA = 1.
Figure 9.26 Buffered Input Capture Timing (Normal Case)
M
m
n
M
n
n + 1
N
M
n
N
n
N + 1
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