HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 274
HD64F3644H
Manufacturer Part Number
HD64F3644H
Description
IC H8 MCU FLASH 32K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644H
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 9 Timers
Timer Output Compare Control Register (TOCR)
TOCR is an 8-bit read/write register that selects the output compare output levels, enables output
compare output, and controls access to OCRA and OCRB.
TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bits 7 to 5 Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4 Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
OCRS selects which register is accessed when this address is written or read. It does not affect the
operation of OCRA and OCRB.
Bit 4: OCRS
0
1
Bit 3 Output Enable A (OEA): Bit 3 enables or disables the timer output controlled by output
compare A.
Bit 3: OEA
0
1
Bit 2 Output Enable B (OEB): Bit 2 enables or disables the timer output controlled by output
compare B.
Bit 2: OEB
0
1
Rev. 6.00 Sep 12, 2006 page 252 of 526
REJ09B0326-0600
Bit
Initial value
Read/Write
Description
OCRA is selected
OCRB is selected
Description
Output compare A output is disabled
Output compare A output is enabled
Description
Output compare B output is disabled
Output compare B output is enabled
7
1
1
6
5
1
OCRS
R/W
4
0
OEA
R/W
3
0
OEB
R/W
2
0
OLVLA
R/W
1
0
(initial value)
(initial value)
(initial value)
OLVLB
R/W
0
0
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