HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 92

IC H8 MCU FLASH 32K 64-QFP

HD64F3644H

Manufacturer Part Number
HD64F3644H
Description
IC H8 MCU FLASH 32K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644H

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 3 Exception Handling
Bit 5 Reserved bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4 SCI1 Interrupt Request Flag (IRRS1)
Bit 4: IRRS1
0
1
Bits 3 to 0 Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.
Interrupt Request Register 3 (IRR3)
Note:
IRR3 is an 8-bit read/write register, in which a corresponding flag is set to 1 by a transition at pin
INT
to write 0 to clear each flag. Upon reset, IRR3 is initialized to H'00.
Bits 7 to 0 INT
Bit n: INTFn
0
1
Rev. 6.00 Sep 12, 2006 page 70 of 526
REJ09B0326-0600
Bit
Initial value
Read/Write
7
to INT
* Only a write of 0 for flag clearing is possible.
0
. The flags are not cleared automatically when an interrupt is accepted. It is necessary
7
INTF7
to INT
R/W *
Description
Clearing condition:
When IRRS1 = 1, it is cleared by writing 0
Setting condition:
When an SCI1 transfer is completed
Description
Clearing condition:
When INTFn = 1, it is cleared by writing 0
Setting condition:
When the designated signal edge is input at pin INT
7
0
0
Interrupt Request Flags (INTF7 to INTF0)
INTF6
R/W *
0
6
INTF5
R/W *
5
0
INTF4
R/W *
4
0
INTF3
R/W *
3
0
INTF2
R/W *
n
2
0
INTF1
R/W *
1
0
(initial value)
(initial value)
(n = 7 to 0)
INTF0
R/W *
0
0

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