HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 116

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Power-Down Modes
Bits 1 and 0
rate (
Bit 1: SA1
0
1
Legend: * Don’t care
5.2
5.2.1
Transition to Sleep (High-Speed) Mode: The system goes from active mode to sleep (high-
speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1
and the MSON and DTON bits in SYSCR2 are all cleared to 0. In sleep (high-speed) mode CPU
operation is halted but the on-chip peripheral functions other than PWM are operational. CPU
register contents are retained.
Transition to Sleep (Medium-Speed) Mode: The system goes from active mode to sleep
(medium-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in
SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is
cleared to 0. In sleep (medium-speed) mode, as in sleep (high-speed) mode, CPU operation is
halted but the on-chip peripheral functions other than PWM are operational. The clock frequency
in sleep (medium-speed) mode is determined by the MA1 and MA0 bits in SYSCR1. CPU register
contents are retained.
5.2.2
Sleep mode is cleared by any interrupt (timer A, timer B1, timer X, timer V, IRQ
to INT
Rev. 6.00 Sep 12, 2006 page 94 of 526
REJ09B0326-0600
Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
W
0
, SCI
/2,
Sleep Mode
Transition to Sleep Mode
Clearing Sleep Mode
W
3
, SCI
/4, or
Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock
1
, or A/D converter), or by input at the RES pin.
Bit 0: SA0
0
1
*
W
/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode.
Description
W
W
W
/8
/4
/2
3
to IRQ
(initial value)
0
, INT
7