HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 235

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Timer Load Register B1 (TLB1)
TLB1 is an 8-bit write-only register for setting the reload value of timer counter B1 (TCB1).
When a reload value is set in TLB1, the same value is loaded into timer counter B1 (TCB1) as
well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in
auto-reload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set
within the range of 1 to 256 input clocks.
The same address is allocated to TLB1 as to TCB1.
Upon reset, TLB1 is initialized to H'00.
9.3.3
Interval Timer Operation: When bit TMB17 in timer mode register B1 (TMB1) is cleared to 0,
timer B1 functions as an 8-bit interval timer.
Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer B1 is selected from seven internal clock
signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits
TMB12 to TMB10 of TMB1.
After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to
overflow, setting bit IRRTB1 to 1 in interrupt request register 1 (IRR1). If IENTB1 = 1 in
interrupt enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCB1 returns to H'00 and starts counting up again.
During interval timer operation (TMB17 = 0), when a value is set in timer load register B1
(TLB1), the same value is set in TCB1.
Note: * For details on interrupts, see section 3.3, Interrupts.
Bit
Initial value
Read/Write
Timer Operation
TLB17
W
7
0
TLB16
W
0
6
TLB15
W
0
5
TLB14
W
4
0
Rev. 6.00 Sep 12, 2006 page 213 of 526
TLB13
W
3
0
TLB12
W
2
0
REJ09B0326-0600
TLB11
Section 9 Timers
W
1
0
TLB10
W
0
0