HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 306

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits).
In 8-bit transfer, data written to SDRL is output from pin SO
(LSB). This data is then replaced by LSB-first data input at pin SI
direction from the most significant bit (MSB) toward the LSB.
In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via
SDRU.
SDRL must be written or read only after data transmission or reception is complete. If this register
is read or written while a data transfer is in progress, the data contents are not guaranteed.
The SDRL value upon reset is undefined.
10.2.3
Data can be sent and received in an 8-bit or 16-bit format, with an internal or external clock
selected as the clock source. Overrun errors can be detected when an external clock is used.
Clock: The serial clock can be selected from a choice of eight internal clocks and an external
clock. When an internal clock source is selected, pin SCK
continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock
signal ( /1024 to /2) selected in bits CKS2 to CKS0 is output continuously from pin SCK
an external clock is used, pin SCK
Data Transfer Format: Figure 10.2 shows the data transfer format. Data is sent and received
starting from the least significant bit, in LSB-first format. Transmit data is output from one falling
edge of the serial clock until the next rising edge. Receive data is latched at the rising edge of the
serial clock.
Rev. 6.00 Sep 12, 2006 page 284 of 526
REJ09B0326-0600
SCK
SO /SI
1
1
1
Operation in Synchronous Mode
Bit 0
Bit 1
Figure 10.2 Transfer Format
1
Bit 2
is the clock input pin.
Bit 3
Bit 4
1
Bit 5
becomes the clock output pin. When
1
starting from the least significant bit
1
, which is shifted in the
Bit 6
Bit 7
1
. When