HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 89

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 6 A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter
interrupt requests.
Bit 6: IENAD
0
1
Bit 5 Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4 SCI1 Interrupt Enable (IENS1): Bit 4 enables or disables SCI1 transfer complete
interrupt requests.
Bit 4: IENS1
0
1
Bits 3 to 0 Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.
Interrupt Enable Register 3 (IENR3)
IENR3 is an 8-bit read/write register that enables or disables INT
Upon reset, IENR3 is initialized to H'00.
Bits 7 to 0 INT
disable INT
Bit n: INTENn
0
1
Bit
Initial value
Read/Write
7
to INT
7
INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0
to INT
R/W
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
Disables SCI1 interrupt requests
Enables SCI1 interrupt requests
Disables interrupt requests from pin INT
Enables interrupt requests from pin INT
Description
Description
0
Description
7
0
interrupt requests.
0
Interrupt Enable (INTEN7 to INTEN0): Bits 7 to 0 enable or
R/W
0
6
R/W
0
5
R/W
4
0
Rev. 6.00 Sep 12, 2006 page 67 of 526
n
n
R/W
3
0
7
to INT
Section 3 Exception Handling
R/W
2
0
0
interrupt requests.
REJ09B0326-0600
R/W
1
0
(initial value)
(initial value)
(initial value)
(n = 7 to 0)
R/W
0
0