HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 272

IC H8 MCU FLASH 32K 64-QFP

HD64F3644H

Manufacturer Part Number
HD64F3644H
Description
IC H8 MCU FLASH 32K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644H

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 9 Timers
Timer Control Register X (TCRX)
TCRX is an 8-bit read/write register that selects the valid edges of the input capture signals,
enables buffering, and selects the FRC clock source.
TCRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7 Input Edge Select A (IEDGA): Bit 7 selects the rising or falling edge of the input capture
A input signal (FTIA).
Bit 7: IEDGA
0
1
Bit 6 Input Edge Select B (IEDGB): Bit 6 selects the rising or falling edge of the input capture
B input signal (FTIB).
Bit 6: IEDGB
0
1
Bit 5 Input Edge Select C (IEDGC): Bit 5 selects the rising or falling edge of the input capture
C input signal (FTIC).
Bit 5: IEDGC
0
1
Rev. 6.00 Sep 12, 2006 page 250 of 526
REJ09B0326-0600
Bit
Initial value
Read/Write
IEDGA
R/W
Description
Falling edge of input capture A is captured
Rising edge of input capture A is captured
Description
Falling edge of input capture B is captured
Rising edge of input capture B is captured
Description
Falling edge of input capture C is captured
Rising edge of input capture C is captured
7
0
IEDGB
R/W
0
6
IEDGC
R/W
5
0
IEDGD
R/W
4
0
BUFEA
R/W
3
0
BUFEB
R/W
2
0
CKS1
R/W
1
0
(initial value)
(initial value)
(initial value)
CKS0
R/W
0
0

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