MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 147
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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5.7 Functional Description
5.7.1 Reset Sources
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Table 5-3
controller.
To protect data integrity, a synchronous reset source is not acted upon
by the reset control logic until the end of the current bus cycle. Reset is
then asserted on the next rising edge of the system clock after the cycle
is terminated. Whenever the reset control logic must synchronize reset
to the end of the bus cycle, the internal bus monitor is automatically
enabled regardless of the BME bit state in the chip configuration module
CCR register. Then, if the current bus cycle is not terminated normally
the bus monitor terminates the cycle based on the length of time
programmed in the BMT field of the CCR register.
Internal single-byte, half-word, or word writes are guaranteed to
complete without data corruption when a synchronous reset occurs.
External writes, including word writes to 16-bit ports, are also
guaranteed to complete.
Asynchronous reset sources usually indicate a catastrophic failure.
Therefore, the reset control logic does not wait for the current bus cycle
to complete. Reset is asserted immediately to the system.
Power on
External RESET pin (not stop mode)
External RESET pin (during stop mode)
Watchdog timer
Loss of clock
Loss of lock
Software
LVD reset
Freescale Semiconductor, Inc.
For More Information On This Product,
defines the sources of reset and the signals driven by the reset
Go to: www.freescale.com
Reset Controller Module
Source
Table 5-3. Reset Source Summary
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Asynchronous
Synchronous
Asynchronous
Reset Controller Module
Functional Description
Type
Advance Information
147
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