MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 159

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.3 OnCE
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
for the OSC to restart is dependent upon the startup time of the crystal
used. Power consumption can be reduced in stop mode by disabling
either or both of these functions via the STMPD bits of the Synthesizer
Control Register (SYNCR). See
Register.
The external CLKOUT signal may be enabled during low-power stop (if
the PLL is still enabled) to support systems using this signal as the clock
source.
The system clocks may be enabled during wakeup from stop mode
without waiting for the PLL to lock. This eliminates the wakeup recovery
time, but at the risk of sending a potentially unstable clock to the system.
It is recommended, if this option is used, that the PLL frequency divider
is set so that the targeted system frequency is no more than half the
maximum allowed. This will allow for any frequency overshoot of the PLL
while still keeping the system clock within specification.
In external clock mode, there are no wait times for the OSC startup or
PLL lock.
During wakeup from stop mode, the FLASH clock will always clock
through 16 cycles before the system clocks are enabled. This allows the
FLASH module time to recover from the low-power mode. Thus,
software may immediately continue to fetch instructions from the FLASH
memory.
The external CLKOUT output pin may be disabled in the low state to
lower power consumption via the disable CLKOUT (DISCLK) bit in the
SYNCR. The external CLKOUT pin function is enabled by default at
reset.
The OnCE logic is clocked using the TCLK input and is not affected by
the system clock. Entering debug mode via the OnCE port (or asserting
the external DE pin) will cause the CPU to exit any low-power mode.
Toggling TCLK during any low-power mode will increase the system
current consumption.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Power Management
11.7.2.1 Synthesizer Control
Peripheral Behavior in Low-Power Modes
Advance Information
Power Management
159