MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 505

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.10.10 Conversion Command Word Table
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
During stop mode, the periodic/interval timer is held in reset. Because
stop mode causes QACR1 and QACR2 to be reset to 0, a valid periodic
or interval timer mode must be written after leaving stop mode to release
the timer from reset.
When QADC debug mode is entered and a periodic or interval timer
mode is selected, the timer counter is reset after the conversion in
progress completes. When the periodic or interval timer mode has been
enabled (the timer is counting), but a trigger event has not been issued,
debug mode takes effect immediately, and the timer is held in reset.
Removal of the QADC debug condition restarts the counter from the
beginning. Refer to
The conversion command word (CCW) table is 64 half-word (128 byte)
long RAM with 10 bits of each entry implemented. The CCW table is
written by the user and is not modified by the QADC. Each CCW
requests the conversion of one analog channel to a digital result. The
CCW specifies the analog channel number, the input sample time, and
whether the queue is to pause after the current CCW. The 10
implemented bits of the CCW can be read and written. The remaining six
bits are unimplemented and read as 0s; write operations have no effect.
Each location in the CCW table corresponds to a location in the result
word table. When a conversion is completed for a CCW entry, the 10-bit
result is written in the corresponding result word entry.
The beginning of queue 1 is the first location in the CCW table. The first
location of queue 2 is specified by the beginning of queue 2 pointer field
(BQ2) in QACR2. To dedicate the entire CCW table to queue 1, place
queue 2 in disabled mode and write BQ2 to 64 or greater. To dedicate
the entire CCW table to queue 2, place queue 1 in disabled mode and
set BQ2 to the first location in the CCW table (CCW0).
Figure 19-43
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
illustrates the operation of the queue structure.
19.5.1 Debug Mode
Queued Analog-to-Digital Converter (QADC)
for more information.
Advance Information
Digital Control
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