MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 531
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.3.6 Transfer Code (TC[2:0])
20.3.7 Read/Write (R/W)
20.3.8 Address Bus (A[22:0])
20.3.9 Enable Byte (EB[3:0])
20.3.10 Chip Selects (CS[3:0])
20.3.11 Output Enable (OE)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The transfer code (TC[2:0]) output signals indicate the data transfer
code for the current bus cycle. See
codes. In single-chip mode and master mode, these pins are configured
as digital I/O (PE2, PE1, PE0) by default.
The read/write (R/W) output signal indicates the direction of the data
transfer on the bus. A logic 1 indicates a read from a slave device and a
logic 0 indicates a write to a slave device.
The address bus (A[22:0]) output signals provide the address for the
current bus transfer.
The enable byte (EB[3:0]) output signals indicate which byte of data is
valid during external cycles.
The chip select (CS[3:0]) output signals select external devices for
external bus transactions.
The output enable (OE) signal indicates when an external device can
drive data during external read cycles.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
20.9.4 Transfer Code (TC[2:0])
External Bus Interface Module (EBI)
Advance Information
Signal Descriptions
for
531
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