MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 251
MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
NOTE:
MFD[2:0] — Multiplication Factor Divider Field
In external clock mode, the MFD[2:0] bits have no effect.
See
LOCRE — Loss of Clock Reset Enable Bit
In external clock mode, the LOCRE bit has no effect.
1. f
2. MFD = 000 not valid for f
3. Default value out of reset
MFD[2:0] contain the binary value of the divider in the PLL feedback
loop. See
applied to the reference frequency. When MFD[2:0] are changed or
the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL
mode, MFD[2:0] are ignored, and the multiplication factor is one.
The LOCRE bit determines how the system handles a loss of clock
condition. When the LOCEN bit is clear, LOCRE has no effect. If the
LOCS flag in SYNSR indicates a loss of clock condition, setting the
LOCRE bit causes an immediate reset. To prevent an immediate
reset, the LOCRE bit must be cleared before entering stop mode with
the PLL disabled.
Freescale Semiconductor, Inc.
sys
000 ( 1)
001 ( 2)
010 ( 4)
011 ( 8)
100 ( 16)
101 ( 32)
110 ( 64)
111 ( 128)
Table
For More Information On This Product,
Table 11-3. System Frequency Multiplier of the Reference
1 = Reset on loss of clock
0 = No reset on loss of clock
= f
ref
x (MFD + 2)/2 exp RFD; f
11-6.
(3)
Go to: www.freescale.com
Table
000
1/16
1/32
1/64
(2x)
Frequency
1/2
1/4
1/8
Clock Module
2
1
11-3. The MFD[2:0] value is the multiplication factor
(2)
ref
3/128
< 3 MHz
3/16
3/32
3/64
001
(3x)
3/2
3/4
3/8
3
(1)
ref
(4x)
1/16
1/32
010
x (MFD + 2) <= 80 MHz, f
1/2
1/4
1/8
in Normal PLL Mode
4
2
1
(3)
5/128
5/16
5/32
5/64
(5x)
011
5/2
5/4
5/8
MFD[2:0]
5
3/16
3/32
3/64
(6x)
100
3/2
3/4
3/8
6
3
Memory Map and Registers
sys
7/128
7/16
7/32
7/64
(7x)
101
7/2
7/4
7/8
7
<= 33 MHz
Advance Information
1/16
(8x)
110
1/2
1/4
1/8
Clock Module
8
4
2
1
9/128
9/16
9/32
9/64
(9x)
111
9/2
9/4
9/8
9
251
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