MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 512
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
19.11.3 Conversion Timing Schemes
Advance Information
512
CWPQ1
Q1 RES
TRIG1
QCLK
CWP
EOC
CONVERSION TIME
QS
Figure 19-46. External Positive Edge Trigger Mode Timing with Pause
= 14 QCLKS
LAST
0
LAST
This section contains some conversion timing examples.
shows the timing for basic conversions where it is assumed that:
Recall that when QS = 0, both queues are disabled; when QS = 8,
queue 1 is active and queue 2 is idle; and when QS = 4; queue 1 is
paused and queue 2 is disabled.
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Freescale Semiconductor, Inc.
8
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Q1 begins with CCW0 and ends with CCW3.
CCW0 has pause bit set.
CCW1 does not have pause bit set.
External trigger rising edge for Q1
CCW4 = BQ2 and Q2 is disabled.
Q1 RES shows relative result register updates.
TIME BETWEEN
Go to: www.freescale.com
TRIGGERS
CCW0
4
CCW0
R0
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
CCW1
CONVERSION TIME
= 14 QCLKS
8
Figure 19-46
CCW2
CCW1
R1
MOTOROLA
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