MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 534

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

External Bus Interface Module (EBI)
20.6 Enable Byte Pins (EB[3:0])
20.7 Bus Master Cycles
Advance Information
534
increment the external address by two bytes, A0 is still driven low, and
the TSIZ[1:0] pins are driven to indicate half-word size.
During any word-size transfer, the EBI always drives the A[1:0] pins low
during a word transfer (except on the second cycle of a word to half-word
port transfer in which A1 is incremented).
The enable byte pins (EB[3:0]) are configurable as byte enables for read
and write cycles, or as write enables for write cycles only. The default
function is byte enable unless there is an active chip-select match with
the WE bit set. In all external cycles when one or more EB pins are
asserted, the encoding corresponds to the external data pins to be used
for the transfer as outlined in
In this subsection, each EBI bus cycle type is defined in terms of actions
associated with a succession of internal states.
Read or write operations may require multiple bus cycles to complete
based on the operand size and target port size. Refer to
Transfer
assumed that only a single bus cycle is required for a transfer.
In the waveform diagrams
transfers are related to clock cycles, independent of the clock frequency.
The external bus states are also noted.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
for more information. In the discussion that follows, it is
Go to: www.freescale.com
Table 20-3. EB[3:0] Assertion Encoding
EB Pin
EB0
EB1
EB2
EB3
(Figure 20-3
Table
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
20-3.
through
External Data Pins
D[31:24]
D[23:16]
D[15:8]
D[7:0]
Figure
20-6), data
20.5 Operand
MOTOROLA