MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 542
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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External Bus Interface Module (EBI)
20.9.3 Show Strobe (SHS)
Advance Information
542
Figure 20-5. Internal (Show) Cycle Followed by External 1-Clock Read
A{22:0], TSIZ[1:0]
NOTE:
CLKOUT
CSE[1:0]
TA, TEA
EB[3:0]
D[31:0]
SHS
R/W
CS
OE
The PEPA and PCDPA bits in the ports must also be set to 1 to obtain
full visibility. The waveforms shown in
cycles.
The show strobe (SHS) pin provides an indication to an external device
(emulator or logic analyzer) when to latch address, TC[2:0], TSIZ[1:0],
R/W, CSE, PSTAT, and data from the external pins. In master and
emulation modes, show cycle strobe (SHS) is enabled coming out of
reset. In master mode this default functionality can be overridden to
make the pin function as digital I/O.
For any external cycle or show cycle, the SHS pin is driven low to
indicate valid address, TC, TSIZ, R/W, CSE, and PSTAT are present at
the pins, and driven back high to indicate valid data. The SHS pin is
driven low and back high only once per external bus cycle. See
Figure 20-5
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
INTERNAL CYCLE
Go to: www.freescale.com
and
A1
Figure
SHOW
20-6.
D1
X1
EXTERNAL READ
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
DATA
A2
Figure 20-5
00
X2
D2
describe show
MOTOROLA
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