MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 502
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
19.10.7.4 Periodic Timer Continuous-Scan Mode
Advance Information
502
The purpose of externally gated continuous-scan mode is to
continuously collect digitized samples while the gate is open and to have
the most recent samples available. It is up to the programmer to ensure
that the gate is not opened so long that an end-of-queue is reached.
In the event that the queue completes before the gate closes, the CF1
flag will set, and the queue will roll over to the beginning and continue
conversions until the gate closes. If the gate remains open and the CF1
flag is not cleared, when the queue completes a second time the TOR1
flag will set and the queue will roll-over again. The queue will continue to
execute until the gate closes or the mode is disabled.
If the gate closes before queue 1 completes execution, the QADC stops
and sets the PF1 bit to indicate an incomplete queue. The CWPQ1 field
can be read to determine the last valid conversion in the queue. If the
gate opens again, execution of queue 1 restarts. The start of queue 1 is
always the first CCW in the CCW table. The condition of the gate is only
sampled after each conversion during queue execution, so closing the
gate for a period less than a conversion time interval does not guarantee
the closure will be captured.
The QADC includes a dedicated periodic timer for initiating a scan
sequence on queue 1 and/or queue 2. A programmable timer interval
ranging from 2
selected. The QCLK period is prescaled down from the MCU clock.
When a periodic timer continuous-scan mode is selected, the timer
begins counting. After the programmed interval elapses, the timer
generated trigger event starts the appropriate queue. The QADC
automatically performs the conversions in the queue until an
end-of-queue condition or a pause is encountered. When a pause
occurs, the QADC waits for the periodic interval to expire again, then
continues with the queue. Once EOQ has been detected, the next trigger
event causes queue execution to restart with the first CCW in the queue.
The periodic timer generates a trigger event whenever the time interval
elapses. The trigger event may cause queue execution to continue
following a pause or queue completion or may be considered a trigger
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
7
to 2
17
times the QCLK period in binary multiples can be
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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