MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 430
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Queued Analog-to-Digital Converter (QADC)
19.5 Modes of Operation
19.5.1 Debug Mode
Advance Information
430
This subsection describes the two modes of operation in which the
QADC does not perform conversions in a regular fashion:
The QDBG bit in the Module Configuration Register (QADCMCR)
governs behavior of the QADC when the CPU enters background debug
mode. When QDBG is clear, the QADC operates normally and is
unaffected by CPU background debug mode. See
Configuration Register
When QDBG is set and the CPU enters background debug mode, the
QADC finishes any conversion in progress and then freezes. This is
QADC debug mode. Depending on when debug mode is entered, the
three possible queue freeze scenarios are:
When the QADC enters debug mode while a queue is active, the current
CCW location of the queue pointer is saved.
Debug mode:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Debug mode
Stop mode
When a queue is not executing, the QADC freezes immediately.
When a queue is executing, the QADC completes the current
conversion and then freezes.
If during the execution of the current conversion, the queue
operating mode for the active queue is changed, or a queue 2
abort occurs, the QADC freezes immediately.
Stops the analog clock
Holds the periodic/interval timer in reset
Prevents external trigger events from being captured
Keeps all QADC registers and RAM accessible
Go to: www.freescale.com
(QADCMCR).
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
19.8.1 QADC Module
MOTOROLA
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