MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 8

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table of Contents
Advance Information
8
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
3.5.3.4
3.5.3.5
3.5.3.6
3.5.3.7
3.5.3.8
3.5.3.9
3.5.3.10
3.5.3.11
3.5.4
3.5.4.1
3.5.4.2
3.5.4.3
3.5.5
3.5.5.1
3.5.5.2
3.5.5.3
3.5.5.4
3.5.6
3.5.6.1
3.5.6.2
3.5.7
Freescale Semiconductor, Inc.
For More Information On This Product,
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Phase-Lock Loop (PLL) and Clock Signals . . . . . . . . . . . . 113
External Memory Interface Signals . . . . . . . . . . . . . . . . . .114
Edge Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Serial Peripheral Interface Module Signals . . . . . . . . . . . . 117
Serial Communications Interface Module Signals . . . . . . . 117
Timer Signals (ICOC1[3:0] and ICOC2[3:0]) . . . . . . . . . . . 118
Reset In (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset Out (RSTOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 113
External Clock In (EXTAL) . . . . . . . . . . . . . . . . . . . . . . .113
Crystal (XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Clock Out (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
PLL Enable (PLLEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . .114
Emulation Mode Chip Selects (CSE[1:0]) . . . . . . . . . . . 115
Transfer Code (TC[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . 115
Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Chip Select (CS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
External Interrupts (INT[7:6]) . . . . . . . . . . . . . . . . . . . . . 116
External Interrupts (INT[5:2]) . . . . . . . . . . . . . . . . . . . . . 116
External Interrupts (INT[1:0]) . . . . . . . . . . . . . . . . . . . . . 116
Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . 117
Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . 117
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Receive Data (RXD1 and RXD2) . . . . . . . . . . . . . . . . . . 117
Transmit Data (TXD1 and TXD2). . . . . . . . . . . . . . . . . . 118
Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . 115
Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . 115
Enable Byte (EB[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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